WO2018120087A1 - Array substrate and method for manufacturing array substrate - Google Patents

Abstract

An array substrate, comprising a substrate (10), a TFT switch (12) formed on the substrate (10), a protective layer (13) covering the substrate (10) and the TFT switch (12) and a pixel electrode (14) being formed on the protective layer (13), the TFT switch (12) comprising a gate insulating layer (121), a channel region (122) located on the gate insulating layer (121) and a source (123) and a drain (125) connected to the channel region (122); the pixel electrode (14) is connected to the source (123) or drain (125) via a through hole (15), the through hole (15) being located on one side of the channel region (122) and the through hole (15) passing through the protective layer (13) and the source (123) or drain (125); also provided is a method for manufacturing the array substrate.

Description

Array substrate and array substrate manufacturing method Technical field

The present invention relates to the field of display panel manufacturing technology, and in particular, to an array substrate and an array substrate manufacturing method.

Background technique

When the light of the display panel is emitted through the backlight panel, not all light can pass through the display panel, such as a signal trace for the panel driver chip, and a TFT (Thin Film Transistor) itself. The conventional pixel electrode and the source are connected in a surface contact manner for conducting current, and the source and the drain are made of an opaque metal material, so when the backlight is illuminated from the back, the pixel electrode and the source are The connection area is reduced in light transmittance due to the opaque metal occlusion affecting the aperture ratio.

Summary of the invention

Based on the above problems, the present application provides an array substrate, which reduces the light shielding area and increases the aperture ratio.

The array substrate of the present application includes a substrate, a TFT switch formed on the substrate, a protective layer covering the substrate and the TFT switch, and a pixel electrode formed on the protective layer, and the TFT switch includes a gate insulation a layer, a channel region on the gate insulating layer, and a source and a drain connected to the channel region, wherein the pixel electrode is connected to the source or the drain through a via, the via Located on one side of the channel region and the via extends through the protective layer and the source or drain.

The present application provides a method for fabricating an array substrate, the method comprising:

Providing a substrate formed with a TFT switch; wherein the TFT switch includes a source and a drain;

Forming a protective layer covering the substrate and the TFT switch;

Forming a photoresist layer having a first opening region on the protective layer, and the first opening region is projected onto one side of the source or the drain;

The protective layer and the source or the drain are dry etched by using the photoresist layer as a mask to form a via hole penetrating the protective layer and the source or the drain in the first opening region;

The photoresist layer is removed, and a pixel electrode layer connected to the source or drain through a via is formed on the protective layer.

The method for fabricating an array substrate provided by the present application further includes: forming a peripheral bridge structure on the substrate, and the peripheral bridge structure comprises a double-layer metal stack structure peripheral bridge metal wire;

Forming an insulating layer and a protective layer covering the substrate and the peripheral bridge structure;

Forming a photoresist layer having a second opening region on the protective layer, and the second opening region is projected onto the peripheral bridge metal line;

Drying the protective layer and the insulating layer with the photoresist layer as a mask to form a gap penetrating the protective layer and the insulating layer in the second opening region;

The photoresist layer is removed.

The array substrate described in the present application forms a via hole penetrating a source or a drain of a metal material on a side of the TFT switch to connect the pixel electrode to the source or the drain, thereby ensuring current transmission while making the via position transparent. The light zone, in turn, increases the aperture ratio of the entire array substrate.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings to be used in the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present application, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic structural view of an array substrate of the present application.

2 is a flow chart of a method of manufacturing an array substrate of the present application.

3 is a flow chart of a method for peripheral bridge structure in the method of fabricating an array substrate of the present application.

4 is a flow chart of a specific embodiment of the method for fabricating the array substrate described in FIGS. 2 and 3.

5 to FIG. 7 are schematic structural views of processes corresponding to the respective steps of the array substrate illustrated in FIG. 4.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application.

The array substrate of the embodiment of the present application may be used for, but not limited to, an OLED display or a liquid crystal display, and the display may be flexible or non-flexible, which is not specifically limited in the embodiment of the present application.

Referring to FIG. 1 , an array substrate according to the present application includes a substrate 10 and is formed on the substrate 10 . a TFT switch 12, a protective layer 13 covering the substrate and the TFT switch, and a pixel electrode 14 formed on the protective layer 13. The TFT switch 12 includes a gate insulating layer 121 and is located at the gate insulating layer 121. The upper channel region 122 and the source 123 and the drain 125 connecting the channel region. In this embodiment, the pixel electrode 14 and the source electrode 123 are connected through a via 15 , the via 15 is located at one side of the channel region 122 and the via 15 extends through the protective layer 13 And the source 123. It can be understood that, depending on the performance selection and design requirements of the array substrate, a via hole may be disposed on the drain for connecting the drain and the pixel electrode.

The array substrate is a TFT array substrate or an LTPS-TFT (Low Temperature Poly Si Thin Film Transistor) array substrate. In the present embodiment, the TFT array substrate is connected to the source electrode and the pixel electrode through via holes as an example.

The TFT switch 12 further includes a gate 120 covered by the gate insulating layer 121, a semiconductor layer 124 corresponding to the gate 120 on the gate insulating layer 121, the source 123 and the drain A pole 125 connecting the two sides of the semiconductor layer 124 constitutes the channel region 122. In this embodiment, the semiconductor layer 124 is made of an amorphous silicon material. In other embodiments, the array substrate is an LTPS-TFT array substrate, and the semiconductor layer is made of a polysilicon material.

Further, the protective layer 13 at the via location is stacked with the source 123 and the gate insulating layer 121. The via 15 penetrates the insulating layer and exposes the gate insulating layer. Floor.

Preferably, the pixel electrode 14 covers the inner surface of the hole of the via hole 15, that is, the via hole 15 penetrates the protective layer 13 and the source electrode 123, and the inner surface of the hole is the source 123. The pixel electrode 14 is connected to the cross-sectional side surface of the source electrode 123 in the cross section and the cross-sectional side surface of the insulating layer.

Further, the via 15 is formed by an etching process. Specifically, after the protective layer 13 is formed, the protective layer 13 and the source 123 are dry etched by a dry etching machine, and the same dry etching is performed in two steps. The protective layer 13 and the source 123 are respectively etched to form a via 15 exposing the gate insulating layer.

The array substrate of the present application forms a via hole on the side of the TFT switch to connect the pixel electrode and the source to ensure current transmission, and the via hole penetrates the source 123 of the metal material, so that the position of the via hole 15 is transparent. The area, in turn, increases the aperture ratio of the entire array substrate. According to the conventional design of the prior art, the area where the pixel electrode is connected to the source is 15%, and then the transparent via is provided here. The increase of the aperture ratio of the array substrate is about 15%, which greatly improves the display of the display screen.

Referring to FIG. 2, the present application provides a method for fabricating an array substrate, the method comprising:

Step S1, providing a substrate formed with a TFT switch; wherein the TFT switch includes a source and a drain;

Step S2, forming a protective layer covering the substrate and the TFT switch;

Step S3, forming a photoresist layer having a first opening region on the protective layer, and the first opening region is projected on one side of the source or the drain; in this embodiment, the first opening region is projected onto the substrate Describe one side of the source.

Step S4, using a photoresist layer as a mask to dry-etch the protective layer and the source (which may also be a drain, depending on the specific arrangement of the array substrate), to form the protective layer and the source through the first opening region or Via of the drain;

In step S5, the photoresist layer is removed, and a pixel electrode layer connected to the source through a via is formed on the protective layer.

In this embodiment, a peripheral bridge structure including a peripheral bridge metal wire is further formed on the substrate. The peripheral bridging structure includes a double-layer metal stack structure peripheral bridging metal line.

Referring to FIG. 3, the method for forming the peripheral bridge structure includes:

Step S101, forming a peripheral bridge structure including a peripheral bridge metal line on the substrate;

Step S102, forming an insulating layer and a protective layer covering the substrate and the peripheral bridge structure;

Step S103, forming a photoresist layer having a second opening region on the protective layer, and the second opening region is projected onto the peripheral bridge metal line;

Step S104, dry etching the protective layer and the insulating layer with the photoresist layer as a mask to form a gap penetrating the protective layer and the insulating layer in the second opening region;

Step S105, removing the photoresist layer.

In fact, the peripheral bridge metal line is formed in the same process as the gate, and the notch and the via are formed in the same process, which will be described below by way of specific embodiments.

Referring to FIG. 4, a via is provided on the source as an example. Step S11, providing a substrate 10 formed with a TFT switch and a peripheral bridge structure; wherein the TFT switch includes a gate electrode 120, a gate insulating layer 121, a channel region, a source electrode 123, and a drain electrode 125. The peripheral bridging structure includes a peripheral bridging metal line layer 150 and an insulating layer covering the peripheral bridging metal line layer 150. The gate electrode 120 and the peripheral bridge metal line 150 are formed in the same process of the same layer, and the gate insulating layer 121 and the insulating layer are in the same layer.

As shown in FIG. 5, step S12, a protective layer 13 of a peripheral bridge metal line 150 covering the peripheral bridge structure of the substrate and the TFT switch is formed.

Referring to FIG. 5 and FIG. 6, step S13, a photoresist layer 20 having a first opening region 21 and a second opening region 22 is formed on the protective layer 13, and the first opening region 21 is projected onto the source. 123 is away from the side of the drain 125; the second opening region 22 is projected onto the peripheral bridge metal line 150.

Referring to FIG. 6 and FIG. 7, step S14, dry etching is performed with the photoresist layer 20 as a mask to form a via 15 penetrating the protective layer 13 and the source 123 opposite to the first opening region 21, The second opening region 22 forms a notch 152 exposing the peripheral bridging metal line 150. In this step, the protective layer is etched by using the photoresist layer 20 as a mask. The via of this embodiment is opened on the source.

In this step, dry etching is performed separately by two different gases. Of course, in other embodiments, it can also be formed by a gas etching. Specifically, the dry etching is performed by using the two different gases respectively: the same dry etching step is performed on the protective layer by using a first etching gas to form a first hole and a first notch, and the first hole and the first notch respectively correspond to the a first opening region and a second opening region; then converting into a second etching gas to continue etching on the source to form a second hole, since the insulating layer covering the peripheral bridge metal line 150 is on the same layer as the source 123 a second notch is formed on the insulating layer, and the first hole and the second hole communicate with each other to form the via hole, and the first notch and the second notch form the notch. The first etching gas is a mixture of carbon tetrafluoride (CF4) and oxygen. The second etching gas is a mixture of sulfur hexafluoride and oxygen.

Therefore, in the actual etching process in which the photoresist layer 20 is used as a mask for dry etching, the preset byproduct concentration range value is further included;

The by-product concentration value generated by the etching is detected by the carbon tetrafluoride when the via and the notch are etched; when the by-product concentration value generated by the etching is within the preset by-product concentration range value, the etching is stopped.

The by-product concentration value generated by the etching includes a by-product concentration value generated by the etching source and a by-product concentration value generated when the peripheral bridges the metal line.

Specifically, when the protective layer and the insulating layer are etched, a concentration of by-products generated by etching having a first concentration range is generated, and when the source is etched and not broken, the first concentration range is increased. The two concentration ranges until the source is broken down to a second concentration range to a predetermined byproduct concentration value.

When the by-product concentration value generated by the etching is within the predetermined by-product concentration range value, the etching is stopped to avoid excessive etching of the peripheral bridge metal line 150.

The gate and peripheral bridge metal lines 150 are a two-layer metal stack structure, wherein a top metal etch rate of the gate is less than a bottom metal, and in fact, the gate 120 and the peripheral bridge metal line 150 are through metal molybdenum and A two-layer aluminum layer is formed in which the metal molybdenum is located on the surface layer of aluminum, and the non-metal is faster than the metal due to etching. During the process of forming the vias by the etched source 123, when the source 123 has not been completely broken down, the top portion of the peripheral bridge metal line 150 has begun to have a loss of by-product concentration, and the effect of setting the two layers is to slow down. The peripheral bridge wire is etched, and the by-product concentration range value is detected in order to stop the etching in time to prevent the peripheral bridge wire 150 from being broken down.

Referring to FIG. 1, step S15, the photoresist layer 20 is removed, and a pixel electrode layer 14 is formed on the protective layer 13, and the pixel electrode 14 is connected to the source electrode 123 through a via 15.

The above is a preferred embodiment of the present application, and it should be noted that those skilled in the art can also make several improvements and refinements without departing from the principles of the present application. These improvements and retouchings are also considered. This is the scope of protection of this application.

Claims (15)

An array substrate, comprising: a substrate, a TFT switch formed on the substrate, a protective layer covering the substrate and the TFT switch, and a pixel electrode formed on the protective layer, wherein the TFT switch includes a gate An insulating layer, a channel region on the gate insulating layer, and a source and a drain connected to the channel region, wherein the pixel electrode is connected to the source or the drain through a via, A hole is located at one side of the channel region and the via extends through the protective layer and the source or drain. The array substrate according to claim 1, wherein said pixel electrode covers an inner surface of said via hole. The array substrate according to claim 1, wherein the TFT switch further comprises a gate covered by the gate insulating layer, and a semiconductor layer corresponding to the gate on the gate insulating layer. The source and drain are connected to both sides of the semiconductor layer to form the channel region. The array substrate according to claim 3, wherein the semiconductor layer is made of one of a polysilicon material, an amorphous silicon material, and a metal oxide. The array substrate according to claim 1, wherein the protective layer covers the gate insulating layer through the via. The array substrate according to claim 1, wherein the pixel electrode, the protective layer, and the gate insulating layer are made of a transparent material. The array substrate according to claim 1, wherein the array substrate further comprises a peripheral bridge structure formed on the substrate, the peripheral bridge structure comprising a peripheral bridge metal line, the gate insulation layer and the The protective layer covers the peripheral bridge metal lines. The array substrate according to claim 7, wherein the peripheral bridge wire is a two-layer metal stack structure, wherein a top metal etch rate of the peripheral bridge wire is less than a bottom metal. The array substrate according to claim 8, wherein the gate is a two-layer metal stack structure, and the gate and the peripheral bridge metal line are formed by the same process. An array substrate manufacturing method, characterized in that the method comprises: Providing a substrate formed with a TFT switch, wherein the TFT switch includes a source and a drain; Forming a protective layer covering the substrate and the TFT switch; Forming a photoresist layer having a first opening region on the protective layer, and the first opening region is projected onto one side of the source or the drain; The protective layer and the source or the drain are dry etched by using the photoresist layer as a mask to form a via hole penetrating the protective layer and the source or the drain in the first opening region; The photoresist layer is removed, and a pixel electrode layer connected to the source or drain through a via is formed on the protective layer. The method of manufacturing an array substrate according to claim 10, further comprising: Forming a peripheral bridging structure on the substrate, the peripheral bridging structure comprising a double-layer metal stack structure peripheral bridging metal line; Forming an insulating layer and a protective layer covering the substrate and the peripheral bridge structure; Forming a photoresist layer having a second opening region on the protective layer, and the second opening region is projected onto the peripheral bridge metal line; Drying the protective layer and the insulating layer with the photoresist layer as a mask to form a gap penetrating the protective layer and the insulating layer in the second opening region; The photoresist layer is removed. The method of fabricating an array substrate according to claim 11, wherein the peripheral bridge metal line is formed in the same process as the gate of the TFT switch; The photoresist layer provided with the second opening region and the photoresist layer provided with the first opening region are the same photoresist layer, and the second opening region is formed in the same process as the first opening region; The gap is formed in the same process as the via. The method of fabricating an array substrate according to claim 12, wherein the dry etching using the photoresist layer as a mask comprises: etching a first hole and forming a first hole on the protective layer using a first etching gas; a gap, and then converted into a second etching gas, continuing etching on the source to form a second hole, forming a second gap on the gate insulating layer, the first hole communicating with the second hole to form the via hole, the first gap The gap is formed with the second gap. The method of fabricating an array substrate according to claim 13 , wherein the peripheral bridge metal line is a two-layer metal stack structure, wherein a top metal etch rate of the peripheral bridge metal line is smaller than an underlying metal; A two-layer metal stack structure in which a top metal etch rate of the gate is less than an underlying metal, and a gate and a peripheral bridge metal line are formed in the same process. The method of manufacturing an array substrate according to claim 14, wherein the method further comprises: preset a byproduct concentration range value; Detecting the by-product concentration value generated by the etching when etching the via hole and the notch; when the etching is generated The etch is stopped when the product concentration value is within the preset byproduct concentration range value.

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