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WO2018120087A1 - Substrat de réseau, et procédé de fabrication de substrat de réseau - Google Patents

Substrat de réseau, et procédé de fabrication de substrat de réseau Download PDF

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Publication number
WO2018120087A1
WO2018120087A1 PCT/CN2016/113657 CN2016113657W WO2018120087A1 WO 2018120087 A1 WO2018120087 A1 WO 2018120087A1 CN 2016113657 W CN2016113657 W CN 2016113657W WO 2018120087 A1 WO2018120087 A1 WO 2018120087A1
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WO
WIPO (PCT)
Prior art keywords
layer
array substrate
protective layer
source
drain
Prior art date
Application number
PCT/CN2016/113657
Other languages
English (en)
Chinese (zh)
Inventor
叶江波
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201680042773.3A priority Critical patent/CN107996002A/zh
Priority to PCT/CN2016/113657 priority patent/WO2018120087A1/fr
Publication of WO2018120087A1 publication Critical patent/WO2018120087A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display panel manufacturing technology, and in particular, to an array substrate and an array substrate manufacturing method.
  • the display panel When the light of the display panel is emitted through the backlight panel, not all light can pass through the display panel, such as a signal trace for the panel driver chip, and a TFT (Thin Film Transistor) itself.
  • the conventional pixel electrode and the source are connected in a surface contact manner for conducting current, and the source and the drain are made of an opaque metal material, so when the backlight is illuminated from the back, the pixel electrode and the source are The connection area is reduced in light transmittance due to the opaque metal occlusion affecting the aperture ratio.
  • the present application provides an array substrate, which reduces the light shielding area and increases the aperture ratio.
  • the array substrate of the present application includes a substrate, a TFT switch formed on the substrate, a protective layer covering the substrate and the TFT switch, and a pixel electrode formed on the protective layer, and the TFT switch includes a gate insulation a layer, a channel region on the gate insulating layer, and a source and a drain connected to the channel region, wherein the pixel electrode is connected to the source or the drain through a via, the via Located on one side of the channel region and the via extends through the protective layer and the source or drain.
  • the present application provides a method for fabricating an array substrate, the method comprising:
  • the TFT switch includes a source and a drain
  • the protective layer and the source or the drain are dry etched by using the photoresist layer as a mask to form a via hole penetrating the protective layer and the source or the drain in the first opening region;
  • the photoresist layer is removed, and a pixel electrode layer connected to the source or drain through a via is formed on the protective layer.
  • the method for fabricating an array substrate provided by the present application further includes: forming a peripheral bridge structure on the substrate, and the peripheral bridge structure comprises a double-layer metal stack structure peripheral bridge metal wire;
  • the photoresist layer is removed.
  • the array substrate described in the present application forms a via hole penetrating a source or a drain of a metal material on a side of the TFT switch to connect the pixel electrode to the source or the drain, thereby ensuring current transmission while making the via position transparent.
  • the light zone in turn, increases the aperture ratio of the entire array substrate.
  • 1 is a schematic structural view of an array substrate of the present application.
  • FIG. 2 is a flow chart of a method of manufacturing an array substrate of the present application.
  • FIG. 3 is a flow chart of a method for peripheral bridge structure in the method of fabricating an array substrate of the present application.
  • FIGS. 4 is a flow chart of a specific embodiment of the method for fabricating the array substrate described in FIGS. 2 and 3.
  • FIG. 5 to FIG. 7 are schematic structural views of processes corresponding to the respective steps of the array substrate illustrated in FIG. 4.
  • the array substrate of the embodiment of the present application may be used for, but not limited to, an OLED display or a liquid crystal display, and the display may be flexible or non-flexible, which is not specifically limited in the embodiment of the present application.
  • an array substrate includes a substrate 10 and is formed on the substrate 10 .
  • the TFT switch 12 includes a gate insulating layer 121 and is located at the gate insulating layer 121.
  • the pixel electrode 14 and the source electrode 123 are connected through a via 15 , the via 15 is located at one side of the channel region 122 and the via 15 extends through the protective layer 13 And the source 123.
  • a via hole may be disposed on the drain for connecting the drain and the pixel electrode.
  • the array substrate is a TFT array substrate or an LTPS-TFT (Low Temperature Poly Si Thin Film Transistor) array substrate.
  • the TFT array substrate is connected to the source electrode and the pixel electrode through via holes as an example.
  • the TFT switch 12 further includes a gate 120 covered by the gate insulating layer 121, a semiconductor layer 124 corresponding to the gate 120 on the gate insulating layer 121, the source 123 and the drain A pole 125 connecting the two sides of the semiconductor layer 124 constitutes the channel region 122.
  • the semiconductor layer 124 is made of an amorphous silicon material.
  • the array substrate is an LTPS-TFT array substrate, and the semiconductor layer is made of a polysilicon material.
  • the protective layer 13 at the via location is stacked with the source 123 and the gate insulating layer 121.
  • the via 15 penetrates the insulating layer and exposes the gate insulating layer. Floor.
  • the pixel electrode 14 covers the inner surface of the hole of the via hole 15, that is, the via hole 15 penetrates the protective layer 13 and the source electrode 123, and the inner surface of the hole is the source 123.
  • the pixel electrode 14 is connected to the cross-sectional side surface of the source electrode 123 in the cross section and the cross-sectional side surface of the insulating layer.
  • the via 15 is formed by an etching process. Specifically, after the protective layer 13 is formed, the protective layer 13 and the source 123 are dry etched by a dry etching machine, and the same dry etching is performed in two steps. The protective layer 13 and the source 123 are respectively etched to form a via 15 exposing the gate insulating layer.
  • the array substrate of the present application forms a via hole on the side of the TFT switch to connect the pixel electrode and the source to ensure current transmission, and the via hole penetrates the source 123 of the metal material, so that the position of the via hole 15 is transparent.
  • the area increases the aperture ratio of the entire array substrate. According to the conventional design of the prior art, the area where the pixel electrode is connected to the source is 15%, and then the transparent via is provided here. The increase of the aperture ratio of the array substrate is about 15%, which greatly improves the display of the display screen.
  • the present application provides a method for fabricating an array substrate, the method comprising:
  • Step S1 providing a substrate formed with a TFT switch; wherein the TFT switch includes a source and a drain;
  • Step S2 forming a protective layer covering the substrate and the TFT switch
  • Step S3 forming a photoresist layer having a first opening region on the protective layer, and the first opening region is projected on one side of the source or the drain; in this embodiment, the first opening region is projected onto the substrate Describe one side of the source.
  • Step S4 using a photoresist layer as a mask to dry-etch the protective layer and the source (which may also be a drain, depending on the specific arrangement of the array substrate), to form the protective layer and the source through the first opening region or Via of the drain;
  • a photoresist layer as a mask to dry-etch the protective layer and the source (which may also be a drain, depending on the specific arrangement of the array substrate), to form the protective layer and the source through the first opening region or Via of the drain;
  • step S5 the photoresist layer is removed, and a pixel electrode layer connected to the source through a via is formed on the protective layer.
  • a peripheral bridge structure including a peripheral bridge metal wire is further formed on the substrate.
  • the peripheral bridging structure includes a double-layer metal stack structure peripheral bridging metal line.
  • the method for forming the peripheral bridge structure includes:
  • Step S101 forming a peripheral bridge structure including a peripheral bridge metal line on the substrate;
  • Step S102 forming an insulating layer and a protective layer covering the substrate and the peripheral bridge structure
  • Step S103 forming a photoresist layer having a second opening region on the protective layer, and the second opening region is projected onto the peripheral bridge metal line;
  • Step S104 dry etching the protective layer and the insulating layer with the photoresist layer as a mask to form a gap penetrating the protective layer and the insulating layer in the second opening region;
  • Step S105 removing the photoresist layer.
  • peripheral bridge metal line is formed in the same process as the gate, and the notch and the via are formed in the same process, which will be described below by way of specific embodiments.
  • Step S11 providing a substrate 10 formed with a TFT switch and a peripheral bridge structure; wherein the TFT switch includes a gate electrode 120, a gate insulating layer 121, a channel region, a source electrode 123, and a drain electrode 125.
  • the peripheral bridging structure includes a peripheral bridging metal line layer 150 and an insulating layer covering the peripheral bridging metal line layer 150.
  • the gate electrode 120 and the peripheral bridge metal line 150 are formed in the same process of the same layer, and the gate insulating layer 121 and the insulating layer are in the same layer.
  • step S12 a protective layer 13 of a peripheral bridge metal line 150 covering the peripheral bridge structure of the substrate and the TFT switch is formed.
  • step S13 a photoresist layer 20 having a first opening region 21 and a second opening region 22 is formed on the protective layer 13, and the first opening region 21 is projected onto the source. 123 is away from the side of the drain 125; the second opening region 22 is projected onto the peripheral bridge metal line 150.
  • step S14 dry etching is performed with the photoresist layer 20 as a mask to form a via 15 penetrating the protective layer 13 and the source 123 opposite to the first opening region 21,
  • the second opening region 22 forms a notch 152 exposing the peripheral bridging metal line 150.
  • the protective layer is etched by using the photoresist layer 20 as a mask.
  • the via of this embodiment is opened on the source.
  • dry etching is performed separately by two different gases.
  • it can also be formed by a gas etching.
  • the dry etching is performed by using the two different gases respectively: the same dry etching step is performed on the protective layer by using a first etching gas to form a first hole and a first notch, and the first hole and the first notch respectively correspond to the a first opening region and a second opening region; then converting into a second etching gas to continue etching on the source to form a second hole, since the insulating layer covering the peripheral bridge metal line 150 is on the same layer as the source 123 a second notch is formed on the insulating layer, and the first hole and the second hole communicate with each other to form the via hole, and the first notch and the second notch form the notch.
  • the first etching gas is a mixture of carbon tetrafluoride (CF4) and oxygen.
  • the second etching gas is a mixture of sulfur hexafluoride
  • the preset byproduct concentration range value is further included;
  • the by-product concentration value generated by the etching is detected by the carbon tetrafluoride when the via and the notch are etched; when the by-product concentration value generated by the etching is within the preset by-product concentration range value, the etching is stopped.
  • the by-product concentration value generated by the etching includes a by-product concentration value generated by the etching source and a by-product concentration value generated when the peripheral bridges the metal line.
  • a concentration of by-products generated by etching having a first concentration range is generated, and when the source is etched and not broken, the first concentration range is increased.
  • the two concentration ranges until the source is broken down to a second concentration range to a predetermined byproduct concentration value is generated.
  • the etching is stopped to avoid excessive etching of the peripheral bridge metal line 150.
  • the gate and peripheral bridge metal lines 150 are a two-layer metal stack structure, wherein a top metal etch rate of the gate is less than a bottom metal, and in fact, the gate 120 and the peripheral bridge metal line 150 are through metal molybdenum and A two-layer aluminum layer is formed in which the metal molybdenum is located on the surface layer of aluminum, and the non-metal is faster than the metal due to etching.
  • the top portion of the peripheral bridge metal line 150 has begun to have a loss of by-product concentration, and the effect of setting the two layers is to slow down.
  • the peripheral bridge wire is etched, and the by-product concentration range value is detected in order to stop the etching in time to prevent the peripheral bridge wire 150 from being broken down.
  • step S15 the photoresist layer 20 is removed, and a pixel electrode layer 14 is formed on the protective layer 13, and the pixel electrode 14 is connected to the source electrode 123 through a via 15.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat de réseau, comprenant un substrat (10), un commutateur TFT (12) formé sur le substrat (10), une couche de protection (13) recouvrant le substrat (10) et le commutateur TFT (12) et une électrode de pixel (14) étant formée sur la couche de protection (13), le commutateur TFT (12) comprenant une couche d'isolation de grille (121), une région de canal (122) située sur la couche d'isolation de grille (121) et une source (123) et un drain (125) connectés à la région de canal (122); l'électrode de pixel (14) est connectée à la source (123) ou au drain (125) par l'intermédiaire d'un trou traversant (15), le trou traversant (15) étant situé sur un côté de la région de canal (122) et le trou traversant (15) passant à travers la couche de protection (13) et la source (123) ou le drain (125) l'invention concerne également un procédé de fabrication du substrat de réseau.
PCT/CN2016/113657 2016-12-30 2016-12-30 Substrat de réseau, et procédé de fabrication de substrat de réseau WO2018120087A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201680042773.3A CN107996002A (zh) 2016-12-30 2016-12-30 阵列基板及阵列基板制造方法
PCT/CN2016/113657 WO2018120087A1 (fr) 2016-12-30 2016-12-30 Substrat de réseau, et procédé de fabrication de substrat de réseau

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/113657 WO2018120087A1 (fr) 2016-12-30 2016-12-30 Substrat de réseau, et procédé de fabrication de substrat de réseau

Publications (1)

Publication Number Publication Date
WO2018120087A1 true WO2018120087A1 (fr) 2018-07-05

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WO (1) WO2018120087A1 (fr)

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CN109616496B (zh) * 2018-11-15 2020-08-11 武汉华星光电半导体显示技术有限公司 Oled触控显示屏的制作方法

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