WO2018121109A1 - Flash storage structure and manufacturing method therefor - Google Patents

Abstract

A flash storage structure and a manufacturing method therefor. The method comprises: depositing a polysilicon layer on a substrate structure (S110); forming, using the polysilicon layer, a floating gate and a field oxide structure covering the floating gate (S120); forming a protective side wall at the corner of the bottom of the floating gate (S130); forming a tunneling oxide layer on the field oxide structure and the floating gate (S140); and forming a control gate on the tunneling oxide layer (S150).

Description

Flash memory storage structure and manufacturing method thereof Technical field

The present invention relates to the field of semiconductor memory technologies, and in particular, to a flash memory storage structure and a method of fabricating the same.

Background technique

The basic unit of the semiconductor memory device is a semiconductor structure which can represent two states of 0 and 1, and generally, a MOS structure which is common to semiconductor devices is employed. The basic structure of the conventional flash memory (FLASH memory) is mostly to add floating gate memory or release charge in the MOS structure to realize the states of 0 and 1.

In the conventional MOS structure used as a basic memory cell, the outer edge of the floating gate is a tip structure, and when the data needs to be erased, the floating gate tip can be discharged by applying a high voltage to the gate to cause electrons to penetrate from the tunneling oxide layer. The control gate releases the charge stored in the floating gate and changes the storage state of the basic storage unit to achieve the purpose of erasing. It can be understood that the thinner the tunneling oxide layer, the more easily electrons tunnel.

However, in the process of the basic memory cell, an intermediate structure covered with a tunneling oxide layer is further formed after the floating gate is formed. Thereafter the intermediate structure undergoes multiple wet etching processes. Due to the instability of the wet etching, more corrosion occurs at the corners of the bottom of the tunneling oxide layer relative to other places, so that the control gate forms a sharp corner there during the subsequent formation of the control gate. Electrons are easily tunneled from the control gate into the floating gate (this process is called anti-tunneling), resulting in erase instability.

Summary of the invention

Based on this, it is necessary to provide a method of manufacturing a flash memory storage structure which can eliminate overetching at the bottom corners of the floating gate and improve the stability of erasing.

A method of manufacturing a flash memory storage structure, comprising:

Depositing a polysilicon layer on the substrate structure;

Forming a floating gate and a field oxide structure overlying the floating gate by using the polysilicon layer;

Forming a protective sidewall at a corner of the bottom of the floating gate;

Forming a tunneling oxide layer on the field oxide structure and the floating gate;

A control gate is formed on the tunnel oxide layer.

In one embodiment, the step of forming a protective sidewall at a corner of the bottom of the floating gate includes:

Depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxide structure; the isolation layer covers the field oxide structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate;

Part of the isolation layer is removed and only the protective sidewalls at the corners of the bottom of the floating gate are retained.

A flash storage structure comprising:

Substrate structure

a floating gate formed on the substrate structure;

Field oxide structure overlying the floating gate;

Protecting the side wall at a corner of the bottom of the floating gate;

Tunneling an oxide layer formed on the floating gate and the field oxygen structure;

A control gate is formed on the tunnel oxide layer.

The flash memory storage structure of the above embodiment and the manufacturing method thereof, by forming a protective sidewall at the bottom corner of the floating gate, and subsequently forming the tunnel oxide layer, even after undergoing multiple wet etching, the bottom corner of the tunnel oxide layer Corroded, it will also be protected from further corrosion by the protective sidewall. The control gate does not form sharp corners. It can effectively prevent electron anti-tunneling. Further, the protective sidewalls are made of materials that are not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only the present invention. For some embodiments, those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.

1 is a schematic diagram of a memory formed using a basic structure having a floating gate;

2a is a schematic structural view of the basic storage unit of FIG. 1;

2b is a schematic structural view of the basic memory cell of FIG. 1 in the presence of a wet etch defect;

3 is a flow chart showing a method of manufacturing a flash memory storage structure according to an embodiment;

4a to 4e are schematic diagrams showing intermediate structures after processing in the steps shown in FIG. 3;

Figure 5 is a flow chart for forming a floating gate;

6a to 6c and 4b are schematic diagrams showing the intermediate structure after the steps in the flow shown in FIG. 5;

Figure 7 is a schematic view showing the structure formed after depositing an isolation layer on the intermediate structure.

detailed description

In order to facilitate the understanding of the present application, the present application will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the application can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the understanding of the disclosure of the present application will be more thorough.

Unless otherwise defined, all technical and scientific terms used herein and the technology belonging to the invention Those skilled in the art generally understand the same meaning. The terminology used in the description of the invention herein is for the purpose of describing the particular embodiments The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

1 is a schematic diagram of a memory formed using a basic structure having a floating gate. As shown in FIG. 2a, it is a schematic structural diagram of such a basic storage unit. The basic memory cell 10 includes a substrate structure 15, a polysilicon floating gate 11 disposed on the substrate 15, a field oxide structure 12 formed on the floating gate 11, and tunneling oxidation overlying the floating gate 11 and the field oxide structure 12. Layer 13, and polysilicon control gate 14 overlying tunneling oxide layer 13. Among them, the floating gate 11 has a tip end 111.

When the basic memory cell 10 is erased, a high voltage is applied to the control gate 14 to discharge the tip of the floating gate 11. The electrons stored in the floating gate 11 penetrate from the tunnel oxide layer 13 to the control gate 14, changing the storage state of the basic memory cell 10 for the purpose of erasing.

In the process of the basic memory cell 10, the control gate 14 forms a sharp corner 141 at the bottom of the tunnel oxide layer 13, as shown in Figure 2b. Electrons are easily tunneled from the control gate 14 into the floating gate 11, resulting in an unstable erase.

The method of the following embodiments can be used to better fabricate flash memory storage structures and avoid the formation of sharp corners at the bottom of the tunnel oxide layer.

3 is a flow chart of a method of fabricating a flash memory storage structure in accordance with an embodiment. The method includes the following steps S110 to S150. 4a to 4e are schematic views of intermediate structures after processing in each step.

Step S110: depositing a polysilicon layer 200 on the substrate structure 100. The substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and a gate oxide layer above the channel region. For the sake of simplicity, these details are not shown in FIGS. 4a to 4e. It is expressly shown that it is represented only by the entire substrate structure 100. This step is a process after the substrate structure 100 is completed. The structure formed after the treatment in this step is as shown in Fig. 4a.

Step S120: forming a floating gate 210 and a field oxide structure 220 overlying the floating gate by using the polysilicon layer 200. The polysilicon layer 200 is processed to form a floating gate 210 and a field oxide structure 220. The structure formed after the treatment in this step is as shown in Fig. 4b. Since the subsequent wet cleaning is performed by a plurality of steps of the wet process, resulting in the recess at the bottom corner of the subsequent tunnel oxide layer 220, or even the corner of the bottom of the floating gate 210, it is necessary to perform the following step S130.

Step S130: forming a protective sidewall 610 at a corner of the bottom of the floating gate 210. The structure formed after the treatment in this step is as shown in Fig. 4c.

Step S140: forming a tunneling oxide layer on the field oxide structure 220 and the floating gate 210. The tunnel oxide layer 300 is a silicon dioxide layer and can be formed by deposition. The structure formed after the treatment in this step is as shown in Fig. 4d.

Step S150: forming a control gate 400 on the tunnel oxide layer 300. The structure formed after the treatment in this step is as shown in Fig. 4e.

In the method of the above embodiment, by forming the protective sidewall 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 220, even after a plurality of wet etching, the bottom corner of the tunnel oxide layer 220 is Corrosion will also be prevented by the protective sidewall 610 from further corrosion. The control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling. Further, the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.

In an embodiment, as shown in FIG. 5, the above step S120 may include the following sub-steps S121-S124. 6a to 6c and 4b are schematic views of intermediate structures after processing in each step.

Sub-step S121: forming a mask layer 500 on the polysilicon layer 200. The mask layer 500 may be a silicon nitride (SiN) layer. The structure formed after the treatment in this step is as shown in Fig. 6a.

Sub-step S122: patterning the mask layer 500 to form a floating gate window 510 to expose a portion of polysilicon Floor. The structure formed after the treatment in this step is as shown in Fig. 6b.

Sub-step S123: oxidative growth is performed in the floating gate window to form a field oxide structure. This step can form the tip of the floating gate while growing the oxygen structure of the field. The structure formed after the treatment in this step is as shown in Fig. 6c.

Sub-step S124: removing the mask layer and etching a polysilicon layer outside the field oxide structure coverage region to form a floating gate. The structure formed after the treatment in this step is as shown in Fig. 4b.

In an embodiment, the above step S130 may include the following sub-steps S131-S132. Description will be made below with reference to Figs. 4b, 7 and 4c.

Step S131: depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxide structure. This intermediate structure is shown in Figure 4b. After the processing in this step, as shown in FIG. 7, the isolation layer 600 covers the field oxide structure 220, the sidewall of the floating gate 210, and the substrate structure 100 that does not cover the floating gate 210. The isolation layer 500 can be made of a silicon nitride material. It can be understood that, by depositing the isolation layer, there will also be a portion of the isolation layer at the corners of the floating gate 210.

Step S132: removing a part of the isolation layer and leaving only the isolation layer located at the corner of the floating gate to form a protective sidewall. The removed portion of the isolation layer includes a portion overlying the surface of the field oxide structure, a portion overlying the sidewall of the floating gate, and a portion overlying the substrate structure. This step can be performed by dry etching. Self-aligned etching is used when etching a portion of the floating gate sidewall. After the processing in this step, the formed structure is as shown in Fig. 4c.

It can be understood that the protective sidewalls can be formed at the corners of the floating gate in other ways, and are not limited to the above manner.

Based on the same inventive concept, a flash memory storage structure is provided. As shown in FIG. 4e, the flash memory structure includes a substrate structure 100, a floating gate 210, a field oxide structure 220, a tunnel oxide layer 300, and a control gate 400 which are sequentially stacked.

The substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and has a gate oxide layer above the channel region, and the floating gate 210 is located on the gate oxide layer. For the sake of simplicity, these detail structures are not explicitly shown in Figure 4e and are represented only by the entire substrate structure 100. A floating gate 210 is formed on the substrate structure 100 and over the channel between the source and drain regions. The floating gate 210 is a polysilicon material. The floating gate 210 has a discharge tip 211. Field oxide structure 220 overlies floating gate 210, and field oxide structure 220 is a silicon dioxide material. A tunnel oxide layer 300 is formed on the floating gate 210 and the field oxide structure 220, and the tunnel oxide layer 300 is a silicon dioxide material. Wherein, at the corner of the bottom of the floating gate 210, a protective sidewall 610 is provided, and the protective sidewall 610 may be made of a material that attenuates electron tunneling, such as a silicon nitride material. The tunnel oxide layer 300 covers the sidewalls of the floating gate 210 and the protective sidewall 610. A control gate 400 is formed on the tunnel oxide layer 300, and the control gate 400 is a polysilicon material. The height of the protective side wall 610 is 1/5 to 1/2 of the height of the floating gate side wall.

The flash memory structure of the above embodiment, by forming the protective sidewall 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 300, even if subjected to multiple wet etching, the bottom corner of the tunnel oxide layer 220 The area is corroded and will also be protected from further corrosion by the protective side wall 610. The control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling. Further, the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. The formed semiconductor device erase is more stable.

The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (17)

A method of manufacturing a flash memory storage structure, comprising: Depositing a polysilicon layer on the substrate structure; Forming a floating gate and a field oxide structure overlying the floating gate by using the polysilicon layer; Forming a protective sidewall at a corner of the bottom of the floating gate; Forming a tunneling oxide layer on the field oxide structure and the floating gate; A control gate is formed on the tunnel oxide layer. The method of claim 1 wherein said step of forming a protective sidewall at a corner of said bottom of said floating gate comprises: Depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxide structure; the isolation layer covers the field oxide structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate; Part of the isolation layer is removed and only the protective sidewalls at the corners of the bottom of the floating gate are retained. The method of claim 2 wherein dry etching and self-alignment are employed in removing a portion of said isolation layer. The method of claim 2 wherein said spacer layer is of a silicon nitride material. The method of claim 1 wherein said step of forming a floating gate and a field oxide structure overlying the floating gate using said polysilicon layer comprises: Forming a mask layer on the polysilicon layer; Graphically forming the mask layer to form a floating gate window to expose a portion of the polysilicon layer; Oxidative growth in the floating gate window to form a field oxide structure; The mask layer is removed and the polysilicon layer outside the field oxide structure footprint is etched to form a floating gate. The method of claim 5 wherein said mask layer is removed and dry etched polycrystalline The silicon layer is formed to form a floating gate. The method of claim 5 wherein said mask layer is a silicon nitride layer. The method according to claim 1, wherein in the step of forming a tunnel oxide layer on the field oxide structure and the floating gate, the tunneling oxide layer is formed by a deposition method. The method of claim 1 wherein the tunneling oxide layer is a silicon dioxide layer. The method of claim 1 wherein forming a substrate structure prior to the step of depositing a polysilicon layer over the substrate structure comprises: Forming a substrate; Forming a source region, a drain region, and a channel region on the substrate; A gate oxide layer is formed over the channel region. A flash storage structure comprising: Substrate structure a floating gate formed on the substrate structure; Field oxide structure overlying the floating gate; Protecting the side wall at a corner of the bottom of the floating gate; Tunneling an oxide layer formed on the floating gate and the field oxygen structure; A control gate is formed on the tunnel oxide layer. The flash memory storage structure of claim 11 wherein said protective sidewall is a material that attenuates electron tunneling. The flash memory storage structure of claim 11 wherein said protective sidewall is a silicon nitride material. The flash memory storage structure according to claim 11, wherein a height of a portion of the protective sidewall covering the floating gate side wall is 1/5 to 1/2 of a height of the floating gate spacer. A flash memory storage structure according to claim 11, wherein said substrate structure comprises a substrate and source and drain regions formed on the substrate, said floating gate being located in a trench of the source region and the drain region Above the road. The flash memory storage structure of claim 11 wherein said tunneling oxide layer is a silicon dioxide material. The flash memory storage structure of claim 11 wherein said control gate is a polysilicon material.

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