[go: up one dir, main page]

WO2018121109A1 - Structure de stockage flash et son procédé de production - Google Patents

Structure de stockage flash et son procédé de production Download PDF

Info

Publication number
WO2018121109A1
WO2018121109A1 PCT/CN2017/110888 CN2017110888W WO2018121109A1 WO 2018121109 A1 WO2018121109 A1 WO 2018121109A1 CN 2017110888 W CN2017110888 W CN 2017110888W WO 2018121109 A1 WO2018121109 A1 WO 2018121109A1
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
layer
forming
substrate
field oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/110888
Other languages
English (en)
Chinese (zh)
Inventor
梁志彬
刘涛
张松
金炎
王德进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Publication of WO2018121109A1 publication Critical patent/WO2018121109A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs

Definitions

  • the present invention relates to the field of semiconductor memory technologies, and in particular, to a flash memory storage structure and a method of fabricating the same.
  • the basic unit of the semiconductor memory device is a semiconductor structure which can represent two states of 0 and 1, and generally, a MOS structure which is common to semiconductor devices is employed.
  • the basic structure of the conventional flash memory (FLASH memory) is mostly to add floating gate memory or release charge in the MOS structure to realize the states of 0 and 1.
  • the outer edge of the floating gate is a tip structure, and when the data needs to be erased, the floating gate tip can be discharged by applying a high voltage to the gate to cause electrons to penetrate from the tunneling oxide layer.
  • the control gate releases the charge stored in the floating gate and changes the storage state of the basic storage unit to achieve the purpose of erasing. It can be understood that the thinner the tunneling oxide layer, the more easily electrons tunnel.
  • an intermediate structure covered with a tunneling oxide layer is further formed after the floating gate is formed. Thereafter the intermediate structure undergoes multiple wet etching processes. Due to the instability of the wet etching, more corrosion occurs at the corners of the bottom of the tunneling oxide layer relative to other places, so that the control gate forms a sharp corner there during the subsequent formation of the control gate. Electrons are easily tunneled from the control gate into the floating gate (this process is called anti-tunneling), resulting in erase instability.
  • a method of manufacturing a flash memory storage structure comprising:
  • a control gate is formed on the tunnel oxide layer.
  • the step of forming a protective sidewall at a corner of the bottom of the floating gate includes:
  • the isolation layer covers the field oxide structure, the sidewall of the floating gate, and the substrate structure not covering the floating gate;
  • Part of the isolation layer is removed and only the protective sidewalls at the corners of the bottom of the floating gate are retained.
  • a flash storage structure comprising:
  • a control gate is formed on the tunnel oxide layer.
  • the flash memory storage structure of the above embodiment and the manufacturing method thereof by forming a protective sidewall at the bottom corner of the floating gate, and subsequently forming the tunnel oxide layer, even after undergoing multiple wet etching, the bottom corner of the tunnel oxide layer Corroded, it will also be protected from further corrosion by the protective sidewall.
  • the control gate does not form sharp corners. It can effectively prevent electron anti-tunneling.
  • the protective sidewalls are made of materials that are not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.
  • FIG. 1 is a schematic diagram of a memory formed using a basic structure having a floating gate
  • FIG. 2a is a schematic structural view of the basic storage unit of FIG. 1;
  • FIG. 2b is a schematic structural view of the basic memory cell of FIG. 1 in the presence of a wet etch defect
  • FIG. 3 is a flow chart showing a method of manufacturing a flash memory storage structure according to an embodiment
  • FIG. 4a to 4e are schematic diagrams showing intermediate structures after processing in the steps shown in FIG. 3;
  • Figure 5 is a flow chart for forming a floating gate
  • 6a to 6c and 4b are schematic diagrams showing the intermediate structure after the steps in the flow shown in FIG. 5;
  • Figure 7 is a schematic view showing the structure formed after depositing an isolation layer on the intermediate structure.
  • FIG. 1 is a schematic diagram of a memory formed using a basic structure having a floating gate. As shown in FIG. 2a, it is a schematic structural diagram of such a basic storage unit.
  • the basic memory cell 10 includes a substrate structure 15, a polysilicon floating gate 11 disposed on the substrate 15, a field oxide structure 12 formed on the floating gate 11, and tunneling oxidation overlying the floating gate 11 and the field oxide structure 12.
  • Layer 13, and polysilicon control gate 14 overlying tunneling oxide layer 13.
  • the floating gate 11 has a tip end 111.
  • control gate 14 forms a sharp corner 141 at the bottom of the tunnel oxide layer 13, as shown in Figure 2b. Electrons are easily tunneled from the control gate 14 into the floating gate 11, resulting in an unstable erase.
  • the method of the following embodiments can be used to better fabricate flash memory storage structures and avoid the formation of sharp corners at the bottom of the tunnel oxide layer.
  • FIG. 3 is a flow chart of a method of fabricating a flash memory storage structure in accordance with an embodiment. The method includes the following steps S110 to S150. 4a to 4e are schematic views of intermediate structures after processing in each step.
  • Step S110 depositing a polysilicon layer 200 on the substrate structure 100.
  • the substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and a gate oxide layer above the channel region. For the sake of simplicity, these details are not shown in FIGS. 4a to 4e. It is expressly shown that it is represented only by the entire substrate structure 100.
  • This step is a process after the substrate structure 100 is completed. The structure formed after the treatment in this step is as shown in Fig. 4a.
  • Step S120 forming a floating gate 210 and a field oxide structure 220 overlying the floating gate by using the polysilicon layer 200.
  • the polysilicon layer 200 is processed to form a floating gate 210 and a field oxide structure 220.
  • the structure formed after the treatment in this step is as shown in Fig. 4b. Since the subsequent wet cleaning is performed by a plurality of steps of the wet process, resulting in the recess at the bottom corner of the subsequent tunnel oxide layer 220, or even the corner of the bottom of the floating gate 210, it is necessary to perform the following step S130.
  • Step S130 forming a protective sidewall 610 at a corner of the bottom of the floating gate 210.
  • the structure formed after the treatment in this step is as shown in Fig. 4c.
  • Step S140 forming a tunneling oxide layer on the field oxide structure 220 and the floating gate 210.
  • the tunnel oxide layer 300 is a silicon dioxide layer and can be formed by deposition.
  • the structure formed after the treatment in this step is as shown in Fig. 4d.
  • Step S150 forming a control gate 400 on the tunnel oxide layer 300.
  • the structure formed after the treatment in this step is as shown in Fig. 4e.
  • the protective sidewall 610 is formed at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 220, even after a plurality of wet etching, the bottom corner of the tunnel oxide layer 220 is Corrosion will also be prevented by the protective sidewall 610 from further corrosion.
  • the control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling.
  • the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. Therefore, the formed semiconductor device erase is more stable.
  • the above step S120 may include the following sub-steps S121-S124.
  • 6a to 6c and 4b are schematic views of intermediate structures after processing in each step.
  • Sub-step S121 forming a mask layer 500 on the polysilicon layer 200.
  • the mask layer 500 may be a silicon nitride (SiN) layer.
  • the structure formed after the treatment in this step is as shown in Fig. 6a.
  • Sub-step S122 patterning the mask layer 500 to form a floating gate window 510 to expose a portion of polysilicon Floor.
  • the structure formed after the treatment in this step is as shown in Fig. 6b.
  • Sub-step S123 oxidative growth is performed in the floating gate window to form a field oxide structure. This step can form the tip of the floating gate while growing the oxygen structure of the field. The structure formed after the treatment in this step is as shown in Fig. 6c.
  • Sub-step S124 removing the mask layer and etching a polysilicon layer outside the field oxide structure coverage region to form a floating gate.
  • the structure formed after the treatment in this step is as shown in Fig. 4b.
  • step S130 may include the following sub-steps S131-S132. Description will be made below with reference to Figs. 4b, 7 and 4c.
  • Step S131 depositing an isolation layer on the intermediate structure after forming the floating gate and the field oxide structure.
  • This intermediate structure is shown in Figure 4b.
  • the isolation layer 600 covers the field oxide structure 220, the sidewall of the floating gate 210, and the substrate structure 100 that does not cover the floating gate 210.
  • the isolation layer 500 can be made of a silicon nitride material. It can be understood that, by depositing the isolation layer, there will also be a portion of the isolation layer at the corners of the floating gate 210.
  • Step S132 removing a part of the isolation layer and leaving only the isolation layer located at the corner of the floating gate to form a protective sidewall.
  • the removed portion of the isolation layer includes a portion overlying the surface of the field oxide structure, a portion overlying the sidewall of the floating gate, and a portion overlying the substrate structure.
  • This step can be performed by dry etching. Self-aligned etching is used when etching a portion of the floating gate sidewall. After the processing in this step, the formed structure is as shown in Fig. 4c.
  • the protective sidewalls can be formed at the corners of the floating gate in other ways, and are not limited to the above manner.
  • the flash memory structure includes a substrate structure 100, a floating gate 210, a field oxide structure 220, a tunnel oxide layer 300, and a control gate 400 which are sequentially stacked.
  • the substrate structure 100 includes a substrate, a source region, a drain region, and a channel region formed on the substrate, and has a gate oxide layer above the channel region, and the floating gate 210 is located on the gate oxide layer.
  • a floating gate 210 is formed on the substrate structure 100 and over the channel between the source and drain regions.
  • the floating gate 210 is a polysilicon material.
  • the floating gate 210 has a discharge tip 211.
  • Field oxide structure 220 overlies floating gate 210, and field oxide structure 220 is a silicon dioxide material.
  • a tunnel oxide layer 300 is formed on the floating gate 210 and the field oxide structure 220, and the tunnel oxide layer 300 is a silicon dioxide material.
  • a protective sidewall 610 is provided, and the protective sidewall 610 may be made of a material that attenuates electron tunneling, such as a silicon nitride material.
  • the tunnel oxide layer 300 covers the sidewalls of the floating gate 210 and the protective sidewall 610.
  • a control gate 400 is formed on the tunnel oxide layer 300, and the control gate 400 is a polysilicon material.
  • the height of the protective side wall 610 is 1/5 to 1/2 of the height of the floating gate side wall.
  • the flash memory structure of the above embodiment by forming the protective sidewall 610 at the bottom corner of the floating gate 210, after the subsequent formation of the tunnel oxide layer 300, even if subjected to multiple wet etching, the bottom corner of the tunnel oxide layer 220 The area is corroded and will also be protected from further corrosion by the protective side wall 610.
  • the control gate 400 does not form sharp corners, and can effectively prevent electrons from tunneling.
  • the protective sidewall 610 is made of a silicon nitride material that is not easily tunneled by electrons, and can also effectively prevent electrons from tunneling. The formed semiconductor device erase is more stable.

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne une structure de stockage flash et son procédé de fabrication. Le procédé comprend : le dépôt d'une couche de polysilicium sur une structure de substrat (S110) ; la formation, à l'aide de la couche de polysilicium, d'une grille flottante et d'une structure d'oxyde de champ couvrant la grille flottante (S120) ; la formation d'une paroi latérale de protection au niveau du coin du bas de la grille flottante (S130) ; la formation d'une couche d'oxyde à effet tunnel sur la structure d'oxyde de champ et la grille flottante (S140) ; et la formation d'une grille de commande sur la couche d'oxyde à effet tunnel (S150).
PCT/CN2017/110888 2016-12-29 2017-11-14 Structure de stockage flash et son procédé de production Ceased WO2018121109A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611249146.5 2016-12-29
CN201611249146.5A CN108257965A (zh) 2016-12-29 2016-12-29 闪存存储结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2018121109A1 true WO2018121109A1 (fr) 2018-07-05

Family

ID=62706935

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/110888 Ceased WO2018121109A1 (fr) 2016-12-29 2017-11-14 Structure de stockage flash et son procédé de production

Country Status (2)

Country Link
CN (1) CN108257965A (fr)
WO (1) WO2018121109A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114005830A (zh) * 2021-10-29 2022-02-01 上海华虹宏力半导体制造有限公司 闪存存储器的制造方法
CN116113240A (zh) * 2022-11-29 2023-05-12 上海华虹宏力半导体制造有限公司 闪存存储器及其制造方法
CN116193859A (zh) * 2022-12-06 2023-05-30 上海华虹宏力半导体制造有限公司 闪存器件及其制造方法
CN116234314A (zh) * 2023-02-28 2023-06-06 上海华虹宏力半导体制造有限公司 Nord闪存存储器的制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111048511B (zh) * 2018-10-15 2022-03-01 无锡华润上华科技有限公司 Flash器件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204034A (ja) * 1995-01-26 1996-08-09 Sanyo Electric Co Ltd 不揮発性半導体記憶装置の製造方法
US6646301B2 (en) * 1999-01-26 2003-11-11 Seiko Epson Corporation Floating gate semiconductor device
US6914290B2 (en) * 2002-01-07 2005-07-05 Samsung Electronics Co., Ltd. Split-gate type nonvolatile memory devices
CN1945798A (zh) * 2005-08-17 2007-04-11 三星电子株式会社 制造非易失性存储器件的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5879993A (en) * 1997-09-29 1999-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride spacer technology for flash EPROM
US6001690A (en) * 1998-02-13 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology
US6908813B2 (en) * 2003-04-09 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology
US7253470B1 (en) * 2006-08-10 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Floating gate with unique profile by means of undercutting for split-gate flash memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204034A (ja) * 1995-01-26 1996-08-09 Sanyo Electric Co Ltd 不揮発性半導体記憶装置の製造方法
US6646301B2 (en) * 1999-01-26 2003-11-11 Seiko Epson Corporation Floating gate semiconductor device
US6914290B2 (en) * 2002-01-07 2005-07-05 Samsung Electronics Co., Ltd. Split-gate type nonvolatile memory devices
CN1945798A (zh) * 2005-08-17 2007-04-11 三星电子株式会社 制造非易失性存储器件的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114005830A (zh) * 2021-10-29 2022-02-01 上海华虹宏力半导体制造有限公司 闪存存储器的制造方法
CN116113240A (zh) * 2022-11-29 2023-05-12 上海华虹宏力半导体制造有限公司 闪存存储器及其制造方法
CN116193859A (zh) * 2022-12-06 2023-05-30 上海华虹宏力半导体制造有限公司 闪存器件及其制造方法
CN116234314A (zh) * 2023-02-28 2023-06-06 上海华虹宏力半导体制造有限公司 Nord闪存存储器的制造方法

Also Published As

Publication number Publication date
CN108257965A (zh) 2018-07-06

Similar Documents

Publication Publication Date Title
US7416945B1 (en) Method for forming a split gate memory device
WO2018121109A1 (fr) Structure de stockage flash et son procédé de production
CN104934427B (zh) 闪存单元及其制造方法
US7253470B1 (en) Floating gate with unique profile by means of undercutting for split-gate flash memory device
CN106298793A (zh) 自对准分栅闪存器件及其制造方法
JP2008504679A (ja) ナノクラスタ電荷蓄積デバイスを形成する方法
US20070023815A1 (en) Non-volatile memory device and associated method of manufacture
US9111871B2 (en) Semiconductor structure and method for forming the same
US6165845A (en) Method to fabricate poly tip in split-gate flash
CN109378314B (zh) 一种闪存器件的制造方法
CN104851886A (zh) 分栅式存储器件及其制造方法
CN104979295A (zh) 嵌入式分栅闪存器件的制造方法
US20050112821A1 (en) Method of manufacturing split-gate memory
CN110047943B (zh) 一种闪存器件及其制造方法
JP2009094452A (ja) 非揮発性メモリ素子及びその製造方法
CN101140877A (zh) 闪速存储器件
US7005348B2 (en) Methods for fabricating semiconductor devices
JP2004056073A (ja) フラッシュメモリの製造方法
CN108122920A (zh) 提高浮栅型闪存擦除效率的方法以及浮栅型闪存
CN101359694B (zh) 闪存及其制造方法
CN109903797B (zh) 分栅快闪存储器的制造方法及分栅快闪存储器
TWI532169B (zh) 記憶體裝置與其形成方法
WO2018121136A1 (fr) Structure de stockage de mémoire flash et son procédé de fabrication
US7544567B2 (en) Method of manufacturing a flash memory device
CN108039323A (zh) 浮栅型闪存的制作方法及集成电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17887968

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17887968

Country of ref document: EP

Kind code of ref document: A1