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WO2018121136A1 - Structure de stockage de mémoire flash et son procédé de fabrication - Google Patents

Structure de stockage de mémoire flash et son procédé de fabrication Download PDF

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Publication number
WO2018121136A1
WO2018121136A1 PCT/CN2017/112452 CN2017112452W WO2018121136A1 WO 2018121136 A1 WO2018121136 A1 WO 2018121136A1 CN 2017112452 W CN2017112452 W CN 2017112452W WO 2018121136 A1 WO2018121136 A1 WO 2018121136A1
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WO
WIPO (PCT)
Prior art keywords
floating gate
forming
layer
field
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/112452
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English (en)
Chinese (zh)
Inventor
梁志彬
张松
刘涛
金炎
王德进
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Publication of WO2018121136A1 publication Critical patent/WO2018121136A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Definitions

  • the present invention relates to the field of semiconductor memory technologies, and in particular, to a flash memory storage structure and a method of fabricating the same.
  • the basic unit of the semiconductor memory device is a semiconductor structure which can represent both 0 and 1. Generally, this basic unit adopts a common MOS structure.
  • the basic structure of the conventional flash memory (FLASH memory) is mostly to add floating gate memory or release charge in the MOS structure to realize the states of 0 and 1.
  • the outer edge of the floating gate is a tip structure.
  • the floating gate tip can be discharged by applying a high voltage to the gate to discharge the charge stored in the floating gate, and the basic change is changed.
  • the storage state of the storage unit is for the purpose of erasing.
  • the tunneling oxide layer at the tip is thick, which is a defect determined by a conventional manufacturing process, which causes data erasure to sometimes fail.
  • a common improvement is to precisely control the thickness at the tip of the floating gate when depositing the tunneling oxide layer.
  • many of the traditional solutions of this kind of thinking are very difficult to control when they are implemented, which will cause waste of manufacturing costs.
  • a method of manufacturing a flash memory storage structure comprising:
  • a control gate is formed on the tunnel oxide layer.
  • a flash storage structure comprising:
  • the floating gate having a discharge tip
  • a field oxide structure overlying the floating gate; wherein the field oxygen structure covers a portion of the floating gate such that a tip end of the floating gate is exposed;
  • a control gate is formed on the tunnel oxide layer.
  • the tip end of the floating gate is exposed, and a gap is filled between the tip end and the field oxygen structure.
  • the tunneling oxide layer is formed, the thickness of the tunneling oxide layer at the tip is substantially the same as the thickness at other locations, and no additional process is required to control the thinning. Thereby electrons are more easily tunneled.
  • the formed semiconductor device erase is more stable.
  • the above method is a re-etching process after forming the field oxygen structure, is compatible with the conventional process, and is simple in operation, so the cost is low.
  • FIG. 1 is a schematic diagram of a memory formed using a basic structure having a floating gate
  • FIG. 2 is a schematic structural view of the basic storage unit of FIG. 1;
  • FIG. 3 is a flow chart showing a method of manufacturing a flash memory storage structure according to an embodiment
  • FIG. 4a to 4e are schematic diagrams showing intermediate structures after processing in the steps shown in FIG. 3;
  • Figure 5 is a flow chart for forming a floating gate
  • 6a to 6c and 4b are schematic diagrams showing the intermediate structure after the steps in the flow shown in Fig. 5.
  • the basic memory cell 10 includes a substrate structure 15, a polysilicon floating gate 11 disposed on the substrate 15, a field oxide structure 12 formed on the floating gate 11, and tunneling oxidation overlying the floating gate 11 and the field oxide structure 12.
  • Layer 13, and overlying the tunneling oxide layer 13 Crystal silicon control gate 14.
  • the floating gate 11 has a tip end 111.
  • the method of the following embodiments can be used to better fabricate a flash memory structure with a thinner tunneling oxide layer at the tip of the floating gate.
  • FIG. 3 is a flow chart of a method of fabricating a flash memory storage structure in accordance with an embodiment. The method includes the following steps S110 to S150. 4a to 4e are schematic views of intermediate structures after processing in each step.
  • Step S110 depositing a polysilicon layer 200 on the substrate structure 100.
  • the substrate structure 100 includes a substrate, a source region formed on the substrate, a drain region and a channel region, and a gate oxide layer above the channel region. For the sake of simplicity, these details are not shown in FIGS. 4a to 4e. It is expressly shown that it is represented only by the entire substrate structure 100.
  • This step is a process after the substrate structure 100 is completed. The structure formed after the treatment in this step is as shown in Fig. 4a.
  • Step S120 forming a floating gate 210 and a field oxide structure 220 overlying the floating gate by using the polysilicon layer 200.
  • the polysilicon layer 200 is processed to form a floating gate 210 and a field oxide structure 220.
  • the floating gate 210 has a tip end 211.
  • the structure formed after the treatment in this step is as shown in Fig. 4b.
  • Step S130 thinning the field oxide structure 220 to expose the tip end 211 of the floating gate 210.
  • the field oxide structure 220 is thinned to obtain a thinned field oxygen structure 220'.
  • a portion of the oxide covering the tip 211 of the floating gate 210 is removed, so that the tip 211 can be exposed.
  • wet etching is employed.
  • the field oxide structure 200 is thinned.
  • the structure formed after the treatment in this step is as shown in Fig. 4c.
  • the thickness of the above thinning is between 2 and 10 nanometers, that is, the tip of the floating gate is exposed by 2 to 10 nanometers with respect to the field oxygen structure. It is not suitable to reduce too much, to prevent the tip 211 from being exposed too much, and is broken in the subsequent process.
  • Step S140 forming a tunnel oxide layer 300 on the thinned field oxide structure 220' and the floating gate 210.
  • the tunnel oxide layer 300 is a silicon dioxide layer and can be formed by deposition.
  • the structure formed after the treatment in this step is as shown in Fig. 4d.
  • Step S150 forming a control gate 400 on the tunnel oxide layer 300.
  • the structure formed after the treatment in this step is as shown in Fig. 4e.
  • the tip end 211 of the floating gate 210 is exposed, and the gap between the tip end 211 and the field oxygen structure 220' is filled.
  • the tunnel oxide layer 300 is formed in step S140, the thickness of the tunnel oxide layer 300 at the tip 211 is substantially the same as the thickness at other positions, and an additional process is not required to control the thinning. Thereby electrons are more easily tunneled. The formed semiconductor device erase is more stable.
  • the above method is a re-etching process after forming the field oxygen structure 220, which is compatible with the conventional process, and is simple in operation, so the cost is low.
  • the above step S120 may include the following sub-steps S121-S124.
  • 6a to 6c and 4b are schematic views of intermediate structures after processing in each step.
  • Sub-step S121 forming a mask layer 500 on the polysilicon layer 200.
  • the mask layer 500 may be a silicon nitride (SiN) layer.
  • the structure formed after the treatment in this step is as shown in Fig. 6a.
  • Sub-step S122 patterning the mask layer 500 to form a floating gate window 510 to expose a portion of the polysilicon layer 200.
  • the structure formed after the treatment in this step is as shown in Fig. 6b.
  • Sub-step S123 thermal oxidation treatment is performed in the floating gate window 510. This step can form the tip end of the floating gate 210 while growing the field oxide structure 220. In other embodiments, the tip of the floating gate 210 can also be formed by dry etching. The structure formed after the treatment in this step is as shown in Fig. 6c.
  • Sub-step S124 removing the mask layer 500 and etching the polysilicon layer 200 outside the field oxide structure 220 to form a floating gate having a tip.
  • the structure formed after the treatment in this step is as shown in Fig. 4b. Specifically, dry etching may be performed using the field oxide structure 220 as a mask to remove the polysilicon layer 200 covered by the field oxide structure 220. This will result in a floating gate with a tip
  • the flash memory structure includes a substrate structure 100, a floating gate 210, a field oxide structure 220', a tunnel oxide layer 300, and a control gate 400 which are sequentially stacked.
  • the substrate structure 100 includes a substrate, a source region formed on the substrate, a drain region and a channel region, and a gate oxide layer over the channel region, and the floating gate 210 is on the gate oxide layer.
  • a floating gate 210 is formed on the substrate structure 100 and over the channel between the source and drain regions.
  • the floating gate 210 is a polysilicon material.
  • the floating gate 210 has a discharge tip 211.
  • Field oxide structure 220' overlies the floating gate 210 and field oxide structure 220' is a silicon dioxide material. Wherein, the field oxide structure 220' covers a portion of the floating gate 210 such that the tip end 211 of the floating gate 210 is exposed.
  • a tunnel oxide layer 300 is formed on the floating gate 210 and the field oxide structure 220', and the tunnel oxide layer 300 is a silicon oxide material.
  • a control gate 400 is formed on the tunnel oxide layer 300, and the control gate 400 is a polysilicon material.
  • the flash memory storage structure of the above embodiment has a fillable gap between the field oxide structure 220' due to the exposure of the tip end 211 of the floating gate 210.
  • the thickness of the tunneling oxide layer 300 formed at the tip end 211 of the tunneling oxide layer 300 is substantially the same as the thickness at other locations, and no additional process is required to control the thinning. Thereby electrons are more easily tunneled.
  • the formed semiconductor device erase is more stable.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne une structure de stockage de mémoire flash et son procédé de fabrication. Le procédé comprend : le dépôt d'une couche de silicium polycristallin (200) sur une structure de substrat (100) ; l'utilisation de la couche de silicium polycristallin (200) pour former une grille flottante (210) et une structure d'oxyde de champ (220) recouvrant la grille flottante (210) ; l'amincissement de la structure d'oxyde de champ (220) pour exposer la pointe de la grille flottante (210) ; la formation d'une couche d'oxyde tunnel (300) sur la structure d'oxyde de champ (300) et la grille flottante (210) ; et la formation d'une grille de commande (400) sur la couche d'oxyde tunnel (300).
PCT/CN2017/112452 2016-12-29 2017-11-23 Structure de stockage de mémoire flash et son procédé de fabrication Ceased WO2018121136A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611248529.0A CN108257962A (zh) 2016-12-29 2016-12-29 闪存存储结构及其制造方法
CN201611248529.0 2016-12-29

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WO2018121136A1 true WO2018121136A1 (fr) 2018-07-05

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115835633A (zh) * 2022-11-29 2023-03-21 上海华虹宏力半导体制造有限公司 一种闪存半导体器件的形成方法
CN116344335A (zh) * 2023-03-29 2023-06-27 上海华虹宏力半导体制造有限公司 闪存器件及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162691A (zh) * 2006-10-09 2008-04-16 上海华虹Nec电子有限公司 用于分栅结构闪存的浮栅制作方法
CN101170082A (zh) * 2006-10-23 2008-04-30 上海华虹Nec电子有限公司 闪存制造工艺方法
CN101207031A (zh) * 2006-12-21 2008-06-25 台湾积体电路制造股份有限公司 记忆单元及其制造方法
WO2013170722A1 (fr) * 2012-05-14 2013-11-21 无锡华润上华科技有限公司 Procédé de fabrication de mémoire flash

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5972753A (en) * 1997-12-04 1999-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash
US5970371A (en) * 1998-07-06 1999-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM
CN106206451B (zh) * 2016-07-27 2019-06-28 上海华虹宏力半导体制造有限公司 分栅式闪存器件制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162691A (zh) * 2006-10-09 2008-04-16 上海华虹Nec电子有限公司 用于分栅结构闪存的浮栅制作方法
CN101170082A (zh) * 2006-10-23 2008-04-30 上海华虹Nec电子有限公司 闪存制造工艺方法
CN101207031A (zh) * 2006-12-21 2008-06-25 台湾积体电路制造股份有限公司 记忆单元及其制造方法
WO2013170722A1 (fr) * 2012-05-14 2013-11-21 无锡华润上华科技有限公司 Procédé de fabrication de mémoire flash

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115835633A (zh) * 2022-11-29 2023-03-21 上海华虹宏力半导体制造有限公司 一种闪存半导体器件的形成方法
CN116344335A (zh) * 2023-03-29 2023-06-27 上海华虹宏力半导体制造有限公司 闪存器件及其制造方法

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