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WO2018125173A1 - Détermination d'intégrité d'isolation sur une puce - Google Patents

Détermination d'intégrité d'isolation sur une puce Download PDF

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Publication number
WO2018125173A1
WO2018125173A1 PCT/US2016/069350 US2016069350W WO2018125173A1 WO 2018125173 A1 WO2018125173 A1 WO 2018125173A1 US 2016069350 W US2016069350 W US 2016069350W WO 2018125173 A1 WO2018125173 A1 WO 2018125173A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive element
voltage
coupled
transistor
dielectric
Prior art date
Application number
PCT/US2016/069350
Other languages
English (en)
Inventor
Suriya Kumar Ashok KUMAR
Rahim KASIM
Charles Augustine
Narendra V. Lakamraju
Balkaran Singh Gill
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/069350 priority Critical patent/WO2018125173A1/fr
Publication of WO2018125173A1 publication Critical patent/WO2018125173A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
    • G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
    • G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages

Definitions

  • the present disclosure relates to integrated circuits and, more specifically, to determination of on-die isolation integrity.
  • multiple conductive elements may be formed on the wafer with dielectric material dielectrically isolating the conductive elements from each other.
  • separation distance among the conductive elements has decreased and monitoring the dielectric isolation among the conductive elements has become more difficult while remaining important for ensuring proper operation of the dies.
  • Legacy procedures for measuring the dielectric isolation, provided by the dielectric material, among the conductive elements involved forming metal via structures throughout the wafer and measuring leakage between the metal via structures and the conductive elements. Scribe line area, pad count, cost, and wafer space limit the number of metal via structures that are formed on the wafer.
  • the legacy procedures required direct access to the wafer to test the dielectric isolation.
  • the manufacturer usually does not have direct access to the wafers to perform further dielectric isolation tests.
  • the dielectric isolation, provided by the dielectric material, among the conductive elements may be reduced.
  • the reduced dielectric isolation may present shorting risks among the conductive elements at voltages and/or frequencies that did not present shorting risks prior to the degradation of the dielectric material. These shorting risks could lead to failures of the devices that could result in damage and/or destruction of the devices.
  • Figure 1 is an example conductive element layout on a portion of die, according to various embodiments.
  • Figure 2 is example isolation integrity test circuitry, according to
  • Figure 3 is an example isolation integrity test procedure with the
  • Figure 4 is an example discharge profile of a device under test, according to various embodiments.
  • Figure 5 is another example measurement circuitry of isolation integrity test circuitry, according to various embodiments.
  • Figure 6 is an example isolation integrity test procedure with the measurement circuitry of Figure 5, according to various embodiments.
  • Figure 7 is an example isolation compensation system, according to
  • Figure 8 is an example isolation compensation procedure, according to various embodiments.
  • Figure 9 is an interposer implementing one or more embodiments of the present disclosure.
  • Figure 10 is a computer device built in accordance with an embodiment of the present disclosure. Detailed Description
  • a semiconductor package may include a device under test (DUT).
  • the DUT may have a first conductive element and a second conductive element, the first conductive element isolated from the second conductive element by a dielectric material.
  • the semiconductor package may further include measurement circuitry coupled to the DUT.
  • the measurement circuitry may apply an initial voltage to the DUT, the initial voltage applied to the first conductive element, and may couple the second conductive element to ground.
  • the measurement circuitry may further determine a time period of discharge for the first conductive element to discharge to a threshold voltage from the initial voltage, and determine an integrity of dielectric isolation between the first conductive element and the second conductive element based on the time period of discharge.
  • Implementations of the disclosed embodiments may be formed or carried out on a substrate, such as a semiconductor substrate.
  • a substrate such as a semiconductor substrate.
  • semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workf unction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and oxygen- containing metal alloys such as conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbon-containing metal alloys such as metal carbides of these metals, for example hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U- shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from materials such as silicon, nitrogen, carbon, and oxygen, for example silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • the dielectric materials may contain elements such as silicon, oxygen, carbon, nitrogen, fluorine, and hydrogen.
  • Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • Figure 1 is an example conductive element layout 100 on a portion of a die 102, according to various embodiments.
  • the die 102 may include a plurality of conductive elements, such as surface contacts 104 (including surface contact 104a and surface contact 104b), embedded contacts 106 (including embedded contact 106a), and via 108.
  • the conductive elements may form a transistor, interconnects, or some combination thereof within the die 102.
  • the conductive elements may be formed of conductive materials, including silver, copper, gold, aluminum, alloys thereof, other materials known to one of ordinary skill in the art to be used for electrical contacts, or some combination thereof.
  • the conductive elements may be electrically conductive allowing the flow of electrical current to transmit through the conductive elements.
  • the conductive elements may be formed as part of forming the die 102 or may be formed on or through the die 102 after formation of the die 102.
  • the die 102 may include dielectric material 110.
  • the dielectric material 110 may be located between two or more of the conductive elements and may
  • the dielectric isolation provided by the dielectric material 110 may prevent flow of electric current among the conductive elements that the dielectric material 110 isolates from each other. Although the dielectric material 110 may be to prevent flow of electric current, a short may occur among the conductive elements based on distances between the conductive elements, an amount of voltage applied to the conductive elements, a frequency of a signal applied to the conductive elements, an integrity of the dielectric material 110 separating the conductive elements, or some combination thereof.
  • the conductive element layout 100 may include one or more surface
  • the conductive element layout 100 includes two surface contacts 104 (surface contact 104a and surface contact 104b) formed on the surface of the die 102 (e.g., on the dielectric material 110).
  • a non- conductive element such as air or a dielectric material, may separate the surface contact 104a and the surface contact 104b.
  • the non-conductive element may dielectrically isolate the surface contact 104a from the surface contact 104b, such that electricity is not to flow between the surface contact 104a and the surface contact 104b through the non-conductive element.
  • the conductive element layout 100 may further include one or more
  • the conductive element layout 100 includes four embedded contacts 106, including embedded contact 106a.
  • the embedded contacts 106 may abut a surface of the die 102 and extend into the die 102 from the surface. The surface that the embedded contacts 106 abut may be opposite to the surface on which the surface contacts 104 are formed.
  • the dielectric material 110 of the die 102 may, at least partially, encompass the embedded contacts 106.
  • the dielectric material 110 may dielectrically isolate the embedded contacts 106 from each other, such that electricity is not to flow among the embedded contacts 106 through the dielectric material 110.
  • the conductive element layout 100 may further include one or more vias 108 formed within the die 102.
  • the vias 108 may couple one or more of the
  • the surface contacts 104 to the embedded contacts 106 may couple one or more of the surface contacts 104 to other surface contacts 104, may couple one or more of the embedded contacts 106 to other embedded contacts 106, or some combination thereof.
  • the via 108 may be formed within the die 102 and may couple the surface contact 104a to the embedded contact 106a.
  • the dielectric material 110 may isolate the surface contact 104a, the via 108, and the embedded contact 106a (collectively referred to as 'the coupled elements') from the surface contact 104b. Although the dielectric material 110 may isolate the coupled elements from the surface contact 104b, there may exist a shorting risk between the via 108 and the surface contact 104b. In particular, a corner of the via 112 may be relatively close to a corner of the surface contact 114.
  • a short may occur between the via 108 and the surface contact 104b if a voltage differential between the via 108 and the surface contact 104b exceeds a threshold voltage, a frequency of a signal applied to the surface contact 104b or the via 108 exceeds a threshold frequency, a combination of the voltage differential and the frequency of the signal exceed a shorting threshold, or some combination thereof. Further, over time and/or operation the dielectric material 110 may degrade, which may cause the threshold voltage, the threshold frequency, and/or the shorting threshold to decrease.
  • locations of the conductive elements may be selected to provide an expected threshold voltage, threshold frequency, and/or shorting threshold
  • actual placement of the conductive elements may vary.
  • the actual threshold voltage, threshold frequency, and/or shorting threshold may be affected by these variances in placement. Further, the actual threshold voltage, threshold frequency, and/or shorting threshold may vary based on dielectric properties of the dielectric material 110 that may be difficult to measure and/or determine.
  • the surface contact 104b and/or the via 108 do not exceed the threshold voltage, threshold frequency, and/or the shorting threshold, it may beneficial to determine or measure the integrity of the dielectric isolation between the conductive elements, which defines the actual threshold voltage, threshold frequency, and shorting threshold. If any of these threshold values is exceeded, the via 108 may short with the surface contact 104b, which may cause failure and/or damage of a die that includes the conductive element layout 100.
  • Figure 2 is example isolation integrity test circuitry 200, according to
  • the isolation integrity test circuitry 200 may be used to determine the integrity of isolation between conductive elements of a device under test (DUT) 202.
  • the conductive element layout 100 (Fig. 1) is one example of the DUT 202, with the coupled elements (the surface contact 104a, the embedded contact 106a, and the via 108 of Fig. 1) being one of the conductive elements of the DUT 202, and the surface contact 104b (Fig. 1) being another of the conductive elements of the DUT 202, the surface contact 104b being isolated from the coupled elements by the
  • the isolation integrity test circuitry 200 may determine the integrity of the isolation, provided by the dielectric material 110, between the coupled elements and the surface contact 104b. While the conductive element layout 100 is one example of the DUT 202, it is to be understood that the DUT may be any device or electrical component that includes at least two conductive elements isolated from each other by a dielectric material, such as a transistor, a circuit region, or some combination thereof.
  • the isolation integrity circuitry 200 may include bias circuitry 204.
  • the bias circuitry 204 may generate a voltage differential between conductive elements of the DUT 202 isolated from each other.
  • the bias circuitry 204 may be located within a same die as the DUT 202. In other embodiments, the bias circuitry 204 may be located within a same package as the DUT 202, in a separate device that couples to the DUT 202, or some combination thereof.
  • the bias circuitry 204 may include a first transistor 206 and a second
  • the first transistor 206 may have one of the source or the drain of the first transistor 206 coupled to one of the conductive elements, herein after the first conductive element, of the DUT 202 and the other of the source or the drain of the first transistor 206 coupled to a power supply.
  • the gate of the first transistor 206 may be coupled to a control input 212, which may control the activation of the first transistor 206.
  • the first transistor 206 When the first transistor 206 is activated, the first transistor 206 may couple the first conductive element to the power supply 210, allowing the power supply 210 to apply a voltage to the first conductive element.
  • the first transistor 206 When the first transistor 206 is deactivated, the first transistor 206 may decouple the first conductive element from the power supply 210, such that the power supply does not apply the voltage to the first conductive element.
  • the first transistor 206 may be a p-channel metal-oxide semiconductor field-effect transistor (MOSFET), with the source of the first transistor 206 coupled to the power supply 210 and the drain of the first transistor 206 coupled to the first conductive element of the DUT 202.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • the second transistor 208 may have one of the source or the drain of the second transistor 208 coupled to another of the conductive elements, hereinafter the second conductive element, of the DUT 202, the second conductive element coupled to the second transistor 208 being isolated from the first conductive element coupled to the first transistor 206.
  • the second transistor 208 may have the other of the source or the drain of the second transistor 208 coupled to ground 214.
  • the gate of the second transistor 208 may be coupled to the control input 212, which may control the activation of the second transistor 208.
  • the second transistor 208 When the second transistor 208 is activated, the second transistor 208 may couple the second conductive element to ground 214.
  • the second transistor 208 When the second transistor 208 is deactivated, the second transistor 208 may decouple the second conductive element from ground 214.
  • the second transistor 206 may be an n-channel MOSFET, with the source of the second transistor 208 coupled to the second conductive element and the drain of the second transistor 208 coupled to ground 214
  • the bias circuitry 204 may further include a capacitor 228 coupled to the first transistor 206 and the first conductive element of the DUT 202.
  • the capacitor 228 may have a relatively large capacitance, such that the capacitor 228 may hold a relatively large charge.
  • the power supply 210 may be coupled to the capacitor 228 and may charge the capacitor 228.
  • the first transistor 206 and the second transistor 208 may be activated at different times based on the control input 212.
  • the bias circuitry 204 may enter a first state, where the first transistor 206 is activated and the second transistor 208 is deactivated.
  • the power supply 210 may apply a voltage to the first conductive element of the DUT 202 and the capacitor 228, the application of the voltage charging the capacitor 216.
  • the second conductive element of the DUT 202 may be decoupled from ground 214, such that the second conductive element may be floating or a voltage of the second conductive element may be defined by the DUT 202 itself or other circuitry and/or components coupled to the DUT 202.
  • the bias circuitry 204 may enter a second state, where first transistor 206 is deactivated and the second transistor 208 is activated.
  • the first conductive element may be decoupled from the power supply 210.
  • the capacitor 228 may have a charge received when the bias circuitry 204 was in the first state and may apply a voltage associated with the charge to the first conductive element while the bias circuitry is in the second state.
  • the second conductive element may be coupled to ground 214.
  • the bias circuitry 204 may enter a third state in response to the control input 212 being a third voltage, the third voltage being a between the first voltage and the second voltage.
  • both the first transistor 206 and the second transistor 208 may be deactivated.
  • the voltages of the first conductive element and the second conductive element may be defined by the DUT 202 itself or other circuitry and/or components coupled to the DUT 202.
  • the isolation integrity test circuitry 200 may further include
  • the measurement circuitry 216 may be coupled to the bias circuitry 204.
  • the measurement circuitry 216 may measure one or more discharge characteristics of the capacitor 228 and may determine the integrity of the isolation between the first conductive element and the second conductive element based on the discharge characteristics. In some embodiments, the measurement circuitry 216 may measure a time for the capacitor 228 to be discharged, either fully or to a
  • the measurement circuitry 216 may measure a frequency at which the bias circuitry 204 transitions between states and determine the integrity of the isolation based on the frequency.
  • the measurement circuitry 216 may include a logical inverter 218.
  • the logical inverter 218 may be coupled to the capacitor 228.
  • the logical inverter 218 may provide a high amount of impedance between the measurement circuitry 216 and the bias circuitry 204, such that current draw by the measurement circuitry 216 on the bias circuitry 204 is limited.
  • the logical inverter 218 may receive the voltage of the capacitor 228 as an input and determine whether the voltage is a logical high or a logical low.
  • the logical inverter 218 may output a logical value that is inverse to the voltage input.
  • the logical inverter 218 may output a logical low value when a voltage of the capacitor 228 exceeds a threshold voltage and output a logical high value when the voltage of the capacitor 228 is below the threshold voltage.
  • the transition voltage of the logical inverter 218 may define the threshold voltage, wherein the threshold voltage may be equal to the transition voltage of the logical inverter 218.
  • the logical inverter 218 may be replaced by a logical buffer that may provide a high amount of impedance.
  • the buffer may receive the voltage of the capacitor 228, determine whether the voltage is a logical high or a logical low, and output the logical high or logical low value of which the voltage is determined to be.
  • the buffer may output a logical high value when the voltage of the capacitor 228 exceeds a threshold voltage and output a logical low value when the voltage of the capacitor 228 is below the threshold voltage.
  • the transition voltage of the buffer may define the threshold voltage, wherein the threshold voltage may be equal to the transition voltage of the buffer.
  • the measurement circuitry 216 may further include a logical NOR 220.
  • the logical NOR 220 may receive the output of the logical inverter 218 and an enable input 222.
  • the enable input 222 may control the operation of the measurement circuitry 216, where the measurement circuitry 216 may measure the discharge characteristics when the enable input 222 is a logical low value and the measurement circuitry 216 may be disabled when the enable input 222 is a logical high value.
  • the logical NOR 220 may output a logical high value when both the output of the logical inverter 218 and the enable input 222 are logical low values and may output a logical low value when either or both of the output of the logical inverter 218 and the enable input 222 are logical high values.
  • the logical NOR 220 may be replaced a logical
  • the measurement circuitry 216 may measure the
  • the enable input 222 is a logical low value and may mask (i.e. output of the logical OR is maintained at a certain value regardless of the value of the output of the logical inverter 218 or the buffer) when the enable input 222 is a logical high value.
  • the output of the logical OR may be equal to the logical value of the output of the logical inverter 218 or buffer.
  • the logical NOR 220 may be omitted and may not be replaced by other logical elements. Further, in these embodiments, the enable input 222 may be omitted. In these embodiments, the measurement circuitry 216 may continuously measure the discharge characteristics and may not be disabled.
  • the measurement circuitry 216 may further include an oscillator 224.
  • the oscillator 224 may oscillate at a defined frequency when a logical high value is applied to the input of the oscillator 224 and may stop oscillating when a logical low value is applied to the input of the oscillator 224. Accordingly, the oscillator 224 may oscillate at the defined frequency when the voltage of the capacitor 228 exceeds the threshold voltage and stop oscillating when the voltage of the capacitor 228 is below the threshold voltage.
  • the oscillator 224 may be a ring oscillator that oscillates at the defined frequency when the logical high value is applied to the input of the oscillator 224.
  • the oscillator 224 may be a harmonic oscillator (such as an
  • the measurement circuitry may further include a counter 226.
  • An input of the counter 226 may be coupled to the output of the oscillator 224.
  • the counter 226 may count a number of oscillations output by the oscillator 224.
  • the counter 226 may maintain the count while the oscillator 224 is not oscillating.
  • the oscillator 224 may further receive a reset input and may reset the count value to an initial count value in response to the reset input being triggered.
  • the oscillator 224 may output the current count value.
  • Figure 3 is an example isolation integrity test procedure 300 with the
  • an initial voltage may be applied to a first conductive element of the DUT 202 (Fig. 2).
  • the initial voltage may be applied by applying a voltage to the control input 212 (Fig. 2) that activates the first transistor 206 (Fig. 2).
  • the second transistor 208 (Fig. 2) may be deactivated, by the voltage applied to the control input 212, while the initial voltage is being applied to the first conductive element.
  • the first transistor 206 When activated, the first transistor 206 may couple the first conductive element to the power supply 210 (Fig. 2), which may charge the capacitor 228 to the initial voltage. The first transistor 206 may remain active for a predetermined period of time, until the capacitor 228 is charged to the initial voltage, or some combination thereof.
  • a voltage of the capacitor 228, being input to the logical inverter 218 (Fig. 2) may exceed the threshold voltage.
  • the oscillator 224 (Fig. 2) may output an oscillating signal having oscillations in response to the voltage of the capacitor 228 exceeding the threshold voltage.
  • the counter 226 (Fig. 2) may count the number of oscillations output in the oscillating signal.
  • the second conductive element of the DUT 202 may be coupled to ground 214.
  • the second conductive element may be coupled to ground 214 by applying a voltage to the control input 212 that activates the second transistor 208.
  • the first transistor 206 may be deactivated, by the voltage applied to the control input 212, when the second conductive element is coupled to ground 214.
  • the voltage of the first conductive element may be equal to the voltage of the capacitor 228 remaining after being charged by the power supply 210 while the first conductive element was coupled to the power supply 210.
  • the oscillator 224 will continue to output the oscillating signal having the oscillations while the voltage of the capacitor 228 continues to exceed the threshold voltage.
  • the counter 226 will continue to count the oscillations of the oscillating signal output by the oscillator 224.
  • the capacitor 228 In a perfect, non-lossy system (where the logical inverter 218 and the transistor 206 would not draw any current from the capacitor 228 and there would be no current leakage across the first transistor 206 and from the first conductive element to the second conductive element), the capacitor 228 would maintain its voltage indefinitely. However, in realistic systems that exist, the logical inverter 218 may draw current from the capacitor 228 and current may leak from the capacitor 228 across the dielectric material, which isolates the first conductive element from the second conductive element, to ground 214. Due to these current draws and leakages, the capacitor 228 may discharge over time causing the voltage of the capacitor 228 to decrease.
  • the voltage of the capacitor 228 and the voltage of the first conductive element may drop below the threshold voltage.
  • the oscillator 224 may cease output of the oscillating signal having the oscillations.
  • the counter 226 may maintain its current count of the number of oscillations output by the oscillator 224.
  • a time period of discharge of the first conductive element is determined.
  • the time period of the discharge may be determined based on the frequency of the oscillations output by the oscillator 224 in the oscillating signal and the count of the number of oscillations maintained by the counter 226 after the voltage of the capacitor 228 has dropped below the threshold voltage.
  • a processor may be coupled to the counter 226 and determine the time period based on the count of the number of oscillations retrieved from the counter 226. For one example, the processor may be aware or determine a frequency of the oscillator 224 to be 100 hertz and retrieve a count value of 1,000 from the counter 226. Based on the frequency and the retrieved count value, the processor may determine that the time period for discharge of the first conductive element is ten seconds.
  • the determination of the time period may be performed in response to detecting that the voltage of the capacitor 228 has decreased below the threshold voltage, the oscillator 224 has ceased output of the oscillating signal, the counter 226 has not incremented its count for a certain period of time, or some combination thereof. In other embodiments, the determination of the time period may occur in response to a request for determination of integrity of dielectric isolation.
  • an integrity of the dielectric isolation may be determined for the dielectric material that isolates the first conductive element from the second conductive element.
  • the processor may compare the determined time period of discharge of the first conductive element to an expected time period for discharge of the first conductive element.
  • the expected time period may be based on an expected amount of current draw by the logical inverter 218 and an expected amount of current leakage from the first conductive element to the second conductive element.
  • the expected time period may be based on a measured time period of discharge upon production of the DUT 202 and the determine time period of discharge may be may be determined after the DUT 202 has been in operation for a period of time.
  • the processor may determine the integrity of the dielectric isolation. In response to determining that the determined time period of discharge is equal or greater than the expected time period for discharge, the processor may determine that the integrity of the dielectric isolation is proper and/or not degraded. In response to determining that the determined time period of discharge is less than the expected time period for discharge, the processor may determine that the integrity of the dielectric isolation is decreased or that the integrity has been degraded. In some embodiments, the processor may further determine a percentage of the decreased or degraded integrity based on the comparison.
  • FIG 4 is an example discharge profile of a device under test, according to various embodiments.
  • the discharge profiles are illustrated on graph 400 that illustrates the voltage of the capacitor 228 (Fig. 2) of the DUT 202 (Fig. 2) on the y-axis versus time on the x-axis.
  • a first discharge profile 402, which may correspond to an expected discharge profile of the capacitor 228, is illustrated by the solid line on the graph 400 and a second discharge profile 404, which may correspond to a measured discharge profile of the capacitor 228, is illustrated by the dashed line on the graph 400.
  • a state transition 406 is illustrated by the dotted line on the graph 400.
  • the state transition 406 may be when the procedure 300 (Fig. 3) transitions from 302 (Fig. 3) to 304 (Fig. 3).
  • the first transistor 206 Prior to the state transition 406, the first transistor 206 (Fig. 2) may be activated, coupling the first conductive element to the power supply 210, which applies the initial voltage to the first conductive element.
  • both the first discharge profile 402 and the second discharge profile 404 may be maintained at the initial voltage prior to the state transition 406.
  • the first transistor 206 may be deactivated, decoupling the first conductive element from the power supply 210, and the second transistor 208 (Fig. 2) may be activated coupling the second conductive element to ground 214.
  • the capacitor 228 (Fig. 2) may be discharging via the current draws and the current leakage, described in relation to Figure 3, which may cause the voltage of the capacitor 228 to decrease.
  • the first discharge profile 402 may decrease at a first rate and the second discharge profile 404 may decrease at a second rate.
  • the second discharge profile 404 decreases at a rate that is greater than the rate at which the first discharge profile 402 decreases, and the second discharge profile 404 reaches a zero voltage earlier in time than the first discharge profile 402.
  • the integrity of the dielectric isolation of the second discharge profile 404 is decreased or has degraded from the first discharge profile 402. If, on the other hand, the second discharge profile 404 were to decrease at the same rate or a lower rate than the first discharge profile, it may be determined that the integrity of the dielectric isolation of the second discharge profile 404 is proper and/or not degraded.
  • FIG 5 is an example measurement circuitry 502 of isolation integrity test circuitry 500, according to various embodiments.
  • the isolation integrity test circuitry 500 may include bias circuitry 204. It is to be understood that the bias circuitry 204 of isolation integrity test circuitry 500 is the same as the bias circuitry 204 of the isolation integrity test circuitry 200 (Fig. 2). As illustrated, the bias circuitry 204 may receive control input 212, which may be coupled to the same components of the bias circuitry 204 as control input 212 (Fig. 2), and output bias circuitry output 504, which may be coupled to the first conductive element of the DUT 202 (Fig. 2), the capacitor 228 (Fig. 2), and the first transistor 206 (Fig. 2).
  • the measurement circuitry 502 may include a series of logical inverters 506, including a first logical inverter 506a and a second logical inverter 506b.
  • the series of logical inverters 506 may include an even number of inverters and is not limited to two inverters.
  • the first logical inverter 506a may receive the bias circuitry output 504 of the bias circuitry 204.
  • the first logical inverter 506a may provide a high amount of impedance between the measurement circuitry 502 and the bias circuitry 204, such that current draw by the measurement circuitry 502 on the bias circuitry 204 is limited.
  • the bias circuitry output 504 may be coupled to the capacitor 228 and may have a voltage equal to the voltage of the capacitor 228.
  • the first logical inverter 506a may determine whether the bias circuitry output 504 is a logic high or logic low and may output an inverse logic value to that of the bias circuitry output 504.
  • the second logical inverter 506b may receive the output value of the first logical inverter 506a and may output an inverse logic value to the output value of the first logical inverter 506a.
  • the output of the second logical inverter 506b may be coupled to the control input 212 and may control activation of the first transistor 206 and the second transistor 208. Further, the output of the second logical inverter 506b may be coupled to a counter 508.
  • the counter 508 may count a number of times that the output of the second logical inverter 506b changes from logic high value to logic low value, changes from logic low value to logic high value, or changes logic value in either direction.
  • Figure 6 is an example isolation integrity test procedure 600 with the
  • an initial voltage may be applied to a first conductive element of the DUT 202.
  • the initial voltage may be applied by applying a voltage to the control input 212 that activates the first transistor 206.
  • the second transistor 208 may be deactivated, by the voltage applied to the control input 212, while the initial voltage is being applied to the first conductive element.
  • the first transistor 206 When activated, the first transistor 206 may couple the first conductive element to the power supply 210, which may charge the capacitor 228. As the capacitor 228 is being charged, the voltage of the first conductive element of the DUT 202 may increase. Initially, the voltage of the capacitor 228, being input to the first logical inverter 506a, may be below a threshold voltage and the first logical inverter 506a may output a logical high value based on the voltage of the capacitor 228 being below the threshold voltage. Based on the first logical inverter 506a outputting a logical high value, the second logical inverter 506b may output a logical low value, which may be provided to the control input 212 in a feedback loop. Based on the control input 212 receiving the logical low value, the first transistor 206 may remain activated, coupling the first conductive element to the power supply 210, and the second transistor 208 may remain deactivated.
  • the second conductive element of the DUT 202 may be coupled to ground 214.
  • the second conductive element may be coupled to ground 214 in response to the capacitor 228 exceeding the threshold voltage.
  • the first logical inverter 506a may transition to output a logical low value.
  • the second logical inverter 506b may transition to output a logical high value, which may be provided to the control input 212 in the feedback loop.
  • the output of the second logical inverter 506b may be provided to the counter 508.
  • the counter 508 may increment a stored count in response to the output of the second logical inverter 506b transitioning to the logical high value.
  • the counter 508 may maintain its count value when the second logical inverter 506b transitions to the logical high value and may increment the count in response to the second logical inverter 506b transitioning to the logical low value, as described further below.
  • the second transistor 208 may be activated, which may couple the second conductive element to ground. Further, when the control input 212 is a logical high value, the first transistor may be
  • deactivated which may decouple the first conductive element from the power supply 210.
  • the voltage of the first conductive element may be equal to the voltage of the capacitor 228 remaining after being charged by the power supply 210 while the first conductive element was coupled to the power supply 210.
  • the capacitor 228 would maintain its voltage indefinitely.
  • the logical inverter 218 may draw current from the capacitor 228 and current may leak from the capacitor 228 across the dielectric material, which isolates the first conductive element from the second conductive element, to ground 214. Due to these current draws and leakages, the capacitor 228 may discharge over time causing the voltage of the capacitor 228 to decrease.
  • the voltage of the capacitor 228 may drop below the threshold voltage.
  • the first logical inverter 506a may transition to output a logical high value and the second logical inverter 506b may transition to output a logical low value.
  • the logical low value output by the second logical inverter 506b may be provided to the control input 212 in a feedback loop. Further, the logical low value output by the second logical inverter 506b may be provided to the counter 508.
  • the counter 508 may increment its count in response to the second logical inverter 506b transitioning to the logical low value, either in addition to or in lieu of the counter 508 incrementing the count in response to the second logical inverter 506b transitioning to the logical high value. In other embodiments, the counter 508 may maintain its count value when the second logical inverter 506b transitions to the logical low value.
  • the initial voltage may be reapplied to the first conductive element.
  • the initial voltage may be reapplied to the first conductive element in response to the output of the second logical inverter 506b transitioning to the logical low value, which provides the logical low value to the control input 212.
  • the first transistor 206 may be activated, which may couple the first conductive element to the power supply 212.
  • the second transistor 208 may be activated, which may decouple the second conductive element from ground 214. With the first transistor 206 activated and the first conductive element coupled to the power supply 212, the capacitor 228 may again begin charging.
  • the voltage of the capacitor 228 may be below the threshold value.
  • the capacitor 228 may charge and the voltage of the capacitor 228 may increase, thereby increasing the voltage of the first conductive element.
  • the voltage of the capacitor 228 may exceed the threshold voltage.
  • the first logical inverter 506a may transition to output a logical low value and the second logical inverter 506b may transition to output a logical high value.
  • the logical high value output by the second logical inverter 506b may be provided to the control input 212 in a feedback loop.
  • the procedure 600 may return to 604, where the second conductive element is coupled to ground 214.
  • the procedure 600 may continue to alternate between 604 and 606 for the duration of an isolation integrity test, until an event occurs (such as expiration of a timer, completion of an amount of cycles between 604 and 606, or some combination thereof) that transitions the procedure 600 to 608, a request is received to transition the procedure 600 to 608, or some combination thereof.
  • the output of the second logical inverter 506b may oscillate between a logical high value and a logical low value.
  • the frequency of the oscillation of the output of the second logical inverter 506b may be based on an amount of time for the capacitor 228 to charge in 606, an amount of time for the capacitor 228 to discharge in 608, or some combination thereof.
  • the counter 508 may count a number of the oscillations of the second logical inverter 506b between the logical high value and the logical low value.
  • the counter 508 may count the number of oscillations based on the detecting transition of the output of the second logical inverter 506b to the logical high value, detecting transition of the output to the logical high value, detecting a transition of the output to the logical high value and a corresponding transition of the output to the logical low value, or some combination thereof.
  • a frequency of the initial voltage is being reapplied to the first conductive element may be determined.
  • the frequency may be determined in response to completion of a duration of an isolation integrity test, an occurrence of an event (such as expiration of a timer, completion of an amount of cycles between 604 and 606, or some combination thereof), a request to determine the frequency, or some
  • the frequency may be determined by one or more processors coupled to the measurement circuitry 502.
  • the processors may retrieve the number of oscillations of the output of the second logical inverter 506b from the counter 508. Further, the processors may know a duration for which the number of oscillations was counted or may be able to determine the duration for which the number of oscillations was counted. Based on the number of oscillations and the duration, the processors may be able to determine the frequency at which the initial voltage was reapplied to the first conductive element.
  • the processors may determine the integrity of the dielectric isolation between the first conductive element and the second conductive element.
  • the processors may determine the integrity based on the determined frequency.
  • the integrity may be based on comparing the determined frequency with an expected frequency of the oscillations of the output of the second logical inverter 506b. If, based on the comparison, the determined frequency is determined to be greater than the expected frequency, the integrity of the dielectric isolation may be determined to be decreased and/or degraded from the expected value. Alternatively, if, based on the comparison, the determined frequency is determined to be equal to or less than the expected frequency, the integrity of the dielectric isolation may be considered to be proper and/or not degraded.
  • isolation integrity test circuitry 200 (Fig. 2) or the isolation integrity test circuitry 500 (Fig. 5) and the corresponding procedure 300 (Fig. 3) or procedure 600 (Fig. 6), respectively, may be used for testing of any circuitry/dies or any situation
  • implementation of the isolation integrity test circuitry 200 or the isolation integrity test circuitry 500 and the corresponding procedures may be beneficial in certain circuitry/dies or certain situations.
  • the isolation integrity test circuitry 200 may be beneficial for use in testing interlayer dielectric (ILD) breakdown
  • ILD interlayer dielectric
  • isolation integrity test circuitry 500 may be beneficial for use in testing gate oxide breakdown (GOX), where current levels may be higher than ILD breakdown.
  • ILD interlayer dielectric
  • GOX gate oxide breakdown
  • both isolation integrity test circuitry 200 and isolation integrity test circuitry 200 may be formed within the same circuitry or on the same die.
  • the isolation integrity test circuitry 200 and the isolation integrity test circuitry 200 may share the same bias circuitry 204 while interchangeable coupling the bias circuitry 204 to the measurement circuitry 216 (Fig. 2) and the measurement circuitry 502 (Fig. 5).
  • FIG 7 is an example of dielectric isolation compensation system 700, according to various embodiments.
  • the dielectric isolation compensation system 700 may include one or more cores, including core 702 as illustrated.
  • Each of the cores may include the same features of the core 702, and while the description of Figure 7 and Figure 8 refers to a single core 702, it is to be understood that the dielectric isolation compensation system 700 may include multiple cores and the described procedures of Figure 7 and Figure 8 may be applied to any of the multiple cores.
  • the core 702 may include a phase lock loop (PLL) 704.
  • the PLL 704 may control the frequencies of signals being provided to devices within the core 702, which may include a DUT, such as DUT 202 (Fig. 2).
  • the PLL 704 may vary the frequencies of the signals based on an input to the PLL 704.
  • the core 702 may further include isolation integrity test circuitry 706, which may be coupled to the DUT.
  • the isolation integrity test circuitry 706 may be the isolation integrity test circuitry 200 (Fig. 2), the isolation integrity test circuitry 500 (Fig. 5), or both.
  • the isolation integrity test circuitry 706 may include a single bias circuitry 204 (Fig. 2) that may be interchangeably coupled to the
  • the dielectric isolation compensation system 700 may include a controller 708.
  • the controller 708 may be coupled to the core 702.
  • the controller 708 may receive a current dielectric health indicator from the isolation integrity test circuitry 706, compare the current dielectric health indicator with one or more prior dielectric health indicators, and, based on the comparison, determine whether to initiate a corrective action.
  • the dielectric health indicators may be dielectric integrity measurements, such as dielectric integrity measurements that may be output by the isolation integrity test circuitry 706.
  • the controller 708 may be implemented in one or more processors and/or circuitry, where the circuitry may be coupled to the processors.
  • the controller 708 may include a dielectric health history table 710.
  • the dielectric health history table 710 may receive dielectric health indicators from the isolation integrity test circuitry 706 and may store one or more dielectric health indicators in the dielectric health history table 710.
  • the dielectric health history table 710 may return a stored dielectric health indicator, an average of the stored dielectric health indicators, a minimum value of the stored dielectric health indicators, a maximum value of the stored dielectric health indicators, or some combination thereof (collectively referred to as 'the prior dielectric health indicator' throughout Figure 7 and Figure 8).
  • the dielectric health history table 710 may be stored in a memory device, such as a memory device of the controller 708.
  • the controller 708 may further include a comparator 712.
  • the comparator 712 may receive the prior dielectric health indicator from the dielectric health history table 710 and the current dielectric health indicator from the isolation integrity test circuitry 706, and may compare the prior dielectric health indicator and the current dielectric health indicator. Based on the comparison, the comparator 712 may output a value that indicates which of the prior dielectric health indicator and the current dielectric health indicator is greater, an amount of difference between the prior dielectric health indicator and the current dielectric health indicator, or some combination thereof.
  • the controller 708 may further include a look up table (LUT) 714.
  • the LUT 714 may include multiple possible comparison result values that may be output by the comparator 712, with each comparison result value having a corresponding entry. Each entry may include an action to be performed in response to receiving an output from the comparator 712 equal to the comparison result value.
  • the actions may include maintaining the current settings (such as voltages and/or frequencies of signals) for the core 702, decreasing voltages supplied to the core 702, increasing voltages supplied to the core 702, decreasing frequencies of signals supplied to the core 702, increasing frequencies of signals supplied to the core 702, or some combination thereof.
  • the LUT 714 may be stored in a memory device, which may be the same memory device in which the dielectric health history table 710 is stored in or a separate memory device.
  • the controller 708 may further include a low drop out regulator (LDO) 716.
  • the LDO 716 may receive a voltage input (Vin) 718 and may utilize the Vin 718 to provide an output voltage (Vout) to the core 702.
  • the Vout of the LDO 716 may be equal to the Vin 718 or may be a value that is a certain percentage of Vin 718 based on an input received by the LDO 716.
  • FIG 8 is an example dielectric isolation compensation procedure 800, according to various embodiments.
  • the dielectric isolation compensation procedure 800 may be implemented by the dielectric isolation compensation system 700 (Fig. 7). Further, in some embodiments, the dielectric isolation compensation procedure 800 may be implemented as instructions stored within a computer readable media, which may be non-transitory. The instructions, when executed by a computer device (such as computer device 1200 (Fig. 12)), may cause the computer device to perform the dielectric isolation compensation procedure 800, or some portion thereof.
  • a dielectric isolation test may be initiated.
  • the dielectric isolation test may initiated in response to a request received by the dielectric isolation compensation system 700. Initiation of the dielectric isolation test may cause the isolation integrity test circuitry 706 (Fig. 7) to perform the isolation integrity test procedure 300 (Fig. 3), the isolation integrity test procedure 600 (Fig. 6), or both, based on which of the isolation integrity test circuitry 200 (Fig. 2) and the isolation integrity test circuitry 500 (Fig. 5) are included in the isolation integrity test circuitry 706 and/or information in the request that cause the dielectric isolation test to be initiated.
  • the resultant dielectric health indicator may be a current dielectric health indicator and may be provided to the comparator 712 (Fig. 7) and/or the dielectric health history table 710 (Fig. 7).
  • the current dielectric health indicator may be compared to the prior dielectric health indicator.
  • the comparator 712 may receive the current dielectric health indicator from the isolation integrity test circuitry 706 and the prior dielectric health indicator from the dielectric health history table 710. The comparator 712 may compare the current dielectric health indicator and the prior dielectric health indicator, and may determine if the current dielectric health indicator and the prior dielectric health indicator are equal or if one of the current dielectric health indicator and the prior dielectric health indicator is greater than the other. In response to the
  • the comparator 712 may output a comparison result value
  • the comparison result value may indicate if the current health of the dielectric material has degraded from the prior health associated with the prior dielectric health indicator, or has remained the same, or improved, as compared to the prior health.
  • the dielectric health history table 710 may receive the current heath indicator and store the current dielectric health indicator within the dielectric health history table 710.
  • the dielectric health history table 710 may update the stored health indicators after the prior dielectric health indicator has been provided to the comparator 712. Updating the stored health indicators may include replacing the prior dielectric health indicator with the current dielectric health indicator, where the current dielectric health indicator will be utilized in future comparisons of dielectric health indicators.
  • the current dielectric health indicator may be added to the dielectric health history table 710 and the prior dielectric health indicator may be updated based on the addition of the current dielectric health indicator. Further, in other
  • the dielectric health history table 710 may determine whether to store the current dielectric health indicator based on the value of the current dielectric health indicator. In 806, it may be determined whether to initiate a corrective action based on the results of the comparison of the current dielectric health indicator with the prior dielectric health indicator.
  • the LUT 714 (Fig. 7) may receive the comparison result value output by the comparator 712. The LUT 714 may compare the comparison result value with possible comparison result values stored in the LUT 714 to determine if one of the possible comparison result values matches the comparison result value and, if there is a match, which of the possible comparison result values matches the comparison result value.
  • the procedure 800 may end or the LUT 714 may output a value that indicates that a corrective action is not to be initiated. If the LUT 714 determines that the comparison result value matches one of the possible comparison result values, the LUT 714 identifies the entry that corresponds to the matching possible comparison result value and determines whether to initiate a corrective action based on the entry. If the LUT 714 determines that the entry does not indicate that corrective action is to be taken, the procedure 800 may end or the LUT 714 may output a value that indicates that a corrective action is not to be initiated.
  • the procedure 800 may continue to 808. In 808, a corrective action may be initiated.
  • the LUT 714 may output a value to the LDO 716 (Fig. 7) and/or the PLL 704 (Fig. 7) that indicates what corrective action is to be initiated.
  • the LDO 716 may change its Vout, which is provided to the core 702 (Fig. 7), based on the value.
  • the LDO 716 may increase the Vout or decrease the Vout based on the value.
  • the LDO 716 may generate the Vout by receiving the Vin 718 (Fig. 7) and generating the Vout from the Vin 718.
  • the LDO 716 may include a voltage divider that generates the Vout.
  • the LDO 716 may increase the Vout in response to the comparison result value indicating that the current health of the dielectric material has improved and may decrease the voltage in response to the comparison result value indicating that the current health has degraded.
  • the PLL 704 may change frequencies of one or more signals provided to the core 702 based on the value.
  • the PLL 704 may decrease the frequency of the signals or increase the frequency of the signals based on the value.
  • the PLL 704 may increase the frequency in response to the comparison result value indicating that the current health of the dielectric material has improved and may decrease the frequency in response to the comparison result value indicating that the current health has degraded.
  • the LDO 716 may change the voltage, the PLL 704 may change the frequency, or both.
  • Figure 9 illustrates an interposer 1000 that includes one or more embodiments described herein.
  • the interposer 1000 may be formed on a same die as the isolation integrity test circuitry 200 (Fig. 2) and/or the isolation integrity test circuitry 500 (Fig. 5), and dielectric isolation of portions of the interposer 1000 may be tested by the isolation integrity test circuitry 200 (Fig. 2) and/or the isolation integrity test circuitry 500 (Fig. 5).
  • the interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004.
  • the first substrate 1002 may be, for instance, an integrated circuit die.
  • the second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004.
  • BGA ball grid array
  • the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000.
  • the first and second substrates 1002/1004 are attached to the same side of the interposer 1000.
  • three or more substrates are interconnected by way of the interposer 1000.
  • the interposer 1000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012.
  • the interposer 1000 may further include embedded devices 1014, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.
  • RF radio-frequency
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000.
  • Figure 10 illustrates a computer device 1200 in accordance with various embodiments of the present disclosure.
  • the computer device 1200 may include the isolation integrity test circuitry 200 (Fig. 2), the isolation integrity test circuitry 500 (Fig. 5), the dielectric isolation compensation system 700 (Fig. 7), or some combination thereof. Further, the computer device 1200 may implement one or more of the procedure 300 (Fig. 3), the procedure 600 (Fig. 6), and the procedure (Fig. 8).
  • the computer device 1200 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices.
  • SoC system-on-a-chip
  • the components in the computer device 1200 include, but are not limited to, an integrated circuit die 1202 and at least one communications logic unit 1208.
  • the communications logic unit 1208 is fabricated within the integrated circuit die 1202 while in other implementations the communications logic unit 1208 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1202.
  • the integrated circuit die 1202 may include a CPU 1204 as well as on-die memory 1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM).
  • eDRAM embedded DRAM
  • SRAM
  • Computer device 1200 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1210 (e.g., DRAM), non-volatile memory 1212 (e.g., ROM or flash memory), a graphics processing unit 1214 (GPU), a digital signal processor 1216, a crypto processor 1242 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1220, at least one antenna 1222 (in some implementations two or more antenna may be used), a display or a touchscreen display 1224, a touchscreen controller 1226, a battery 1228 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1228, a compass 1230, a motion coprocessor or sensors 1232 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown),
  • the computer device 1200 includes a radio that is used to
  • the computer device 1200 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.
  • the communications logic unit 1208 enables wireless communications for the transfer of data to and from the computer device 1200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 1208 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computer device 1200 may include a plurality of communications logic units 1208. For instance, a first communications logic unit 1208 may be dedicated to shorter range wireless
  • a second communications logic unit 1208 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1204 of the computer device 1200 includes one or more devices, such as the isolation integrity test circuitry 200 (Fig. 2), the isolation integrity test circuitry 500 (Fig. 5), the dielectric isolation compensation system 700 (Fig. 7), or some combination thereof.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 1208 may also include one or more devices, such as transistors or metal interconnects that are formed in accordance with embodiments described herein.
  • the computer device 1200 may contain one or more devices, such as the isolation integrity test circuitry 200 (Fig. 2), the isolation integrity test circuitry 500 (Fig. 5), the dielectric isolation compensation system 700 (Fig. 7), or some combination thereof.
  • the computer device 1200 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computer device 1200 may be any other electronic device that processes data.
  • Example 1 may include a semiconductor package, comprising a device under test (DUT), the DUT having a first conductive element and a second conductive element, the first conductive element isolated from the second conductive element by a dielectric material and measurement circuitry coupled to the DUT, the measurement circuitry to: apply an initial voltage to the DUT, the initial voltage applied to the first conductive element, couple the second conductive element to ground, determine a time period of discharge for the first conductive element to discharge to a threshold voltage from the initial voltage, and determine an integrity of dielectric isolation between the first conductive element and the second conductive element based on the time period of discharge.
  • DUT device under test
  • Example 2 may include the semiconductor package of example 1, wherein the measurement circuitry includes a capacitor coupled to the first conductive element, wherein the measurement circuitry is to further: couple the first conductive element to a power supply that supplies the initial voltage to the first conductive element, a capacitor coupled to the first conductive element to be charged to the initial voltage when the first conductive element is coupled to the power supply, and decouple the first conductive element from the power supply when the capacitor is fully charged.
  • Example 3 may include the semiconductor package of example 2, wherein the measurement circuitry is to couple the second conductive element to ground.
  • Example 4 may include the semiconductor package of example 3, wherein the measurement circuitry is to further couple the second conductive element to ground at substantially a same time as the first conductive element is decoupled from the power supply.
  • Example 5 may include the semiconductor package of any one of the examples 1-4, wherein the measurement circuitry is to further: output an oscillating signal having oscillations at a constant frequency when a voltage of the first conductive element is greater than the threshold voltage and to cease output of the oscillating signal when the voltage is less than the threshold voltage, and count a number of the oscillations in the oscillating signal output by the oscillator, wherein the integrity of the dielectric isolation is determined based on the number of the oscillations.
  • Example 6 may include the semiconductor package of example 5, wherein the measurement circuitry includes an inverter coupled to the first conductive element, the threshold voltage defined by a transition voltage of the inverter, an output of the inverter coupled to the oscillator and to cause the oscillator to output the oscillating signal when the voltage of the first conductive element is greater than the threshold voltage and to cause the oscillator to cease output of the oscillating signal when the voltage of the first conductive element is less than the threshold voltage.
  • the measurement circuitry includes an inverter coupled to the first conductive element, the threshold voltage defined by a transition voltage of the inverter, an output of the inverter coupled to the oscillator and to cause the oscillator to output the oscillating signal when the voltage of the first conductive element is greater than the threshold voltage and to cause the oscillator to cease output of the oscillating signal when the voltage of the first conductive element is less than the threshold voltage.
  • Example 7 may include the semiconductor package of any one of the examples 1-4, wherein the DUT is a transistor, and wherein the first conductive element is a first contact of the transistor and the second conductive element is a second contact of the transistor.
  • Example 8 may include a semiconductor package, comprising a device under test
  • DUT the DUT having a first conductive element and a second conductive element, the first conductive element isolated from the second conductive element by a dielectric material, and measurement circuitry coupled to the DUT, the measurement circuitry to: apply an initial voltage to the DUT, the initial voltage applied to the first conductive element, couple the second conductive element to ground, reapply the initial voltage to the first conductive element when a voltage of the first conductive element discharges below a threshold voltage, determine a frequency of the initial voltage is being reapplied to the first conductive element, and determining an integrity of dielectric isolation between the first conductive element and the second conductive element based on the frequency.
  • Example 9 may include the semiconductor package of example 8, wherein the measurement circuitry is to further decouple the second conductive element from ground while the initial voltage is reapplied to the first conductive element, and recouple the second conductive element to ground in response to completion of the reapplication of the initial voltage to the first conductive element.
  • Example 10 may include the semiconductor package of example 8, wherein the application of the initial voltage includes to couple the first conductive element to a power supply that supplies the initial voltage to the first conductive element, a capacitor coupled to the first conductive element to be charged to the initial voltage when the first conductive element is coupled to the power supply, and decouple the first conductive element from the power supply when the capacitor is fully charged.
  • Example 11 may include the semiconductor package of example 8, wherein the reapplication of the initial voltage includes to couple the first conductive element to the power supply in response to the voltage of the first conductive element discharging below the threshold voltage, a capacitor coupled to the first conductive element to be charged to the initial voltage when the first conductive element is coupled to the power supply, and decouple the first conductive element from the power supply when the capacitor is fully charged.
  • Example 12 may include the semiconductor package of any one of the examples
  • the measurement circuitry is to further couple the second conductive element to ground when the first conductive element is decoupled from the power supply.
  • Example 13 may include the semiconductor package of example 12, wherein the measurement circuitry couples the second conductive element to ground at
  • Example 14 may include the semiconductor package of any one of the examples 8-11, wherein the measurement circuitry is to further count a number of reapplications of the initial voltage to the first conductive element for a time period and determine the frequency based on the number of reapplications of the initial voltage and the time period.
  • Example 15 may include the semiconductor package of example 14, wherein the measurement circuitry includes a series of inverters coupled to the first conductive element, wherein the threshold voltage is defined by transition voltages of series of inverters, the series inverters to increment the number of reapplications in response to the voltage of the first conductive element discharging below the threshold voltage.
  • Example 16 may include the semiconductor package of any one of the examples 8-11, wherein the DUT is a transistor, and wherein the first conductive element is a first contact of the transistor and the second conductive element is a second contact of the transistor.
  • Example 17 may include a method of determining integrity of dielectric isolation within a die, comprising applying an initial voltage to a device under test (DUT) of the die, the initial voltage applied to a first conductive element of the DUT, coupling a second conductive element of the DUT to ground, the second conductive element isolated from the first conductive element by a dielectric material, determining a time period of discharge for the first conductive element to discharge to a threshold voltage from the initial voltage, and determining the integrity of dielectric isolation between the first conductive element and the second conductive element based on the time period of discharge.
  • DUT device under test
  • Example 18 may include the method of example 17, wherein applying the initial voltage to the first conductive element includes activating a transistor coupled to the first conductive element to couple the first conductive element to a power supply that supplies the initial voltage to the first conductive element and charges a capacitor coupled to the first conductive element to the initial voltage, and deactivating the transistor to decouple the first conductive element from the power supply, the time period of discharge beginning when the transistor is deactivated.
  • Example 19 may include the method of example 18, wherein the transistor is a first transistor, and wherein coupling the second conductive element of the DUT to ground includes activating a second transistor coupled to the second conductive element to couple the second conductive element to ground.
  • Example 20 may include the method of example 19, wherein activation of the second transistor occurs at substantially a same time as the first transistor is deactivated.
  • Example 21 may include the method of any one of the examples 17-20, wherein determining the time period of discharge for the first conductive element includes activating an oscillator when a voltage of the first conductive element is greater than the threshold voltage, the oscillator to output an oscillating signal having oscillations at a constant frequency when the oscillator is activated, counting, by a counter, a number of the oscillations in the oscillating signal output by the oscillator, deactivating the oscillator when the voltage of the first conductive element is less than the threshold voltage, the oscillator to cease output of the oscillating signal when the oscillator is deactivated, and determining the time period of discharge based on the number of the oscillations counted by the counter.
  • Example 22 may include the method of example 21, wherein the threshold voltage is defined by a transition voltage of an inverter coupled to the first conductive element, the inverter to activate the oscillator when the voltage of the first conductive element is greater than the threshold voltage and to deactivate the oscillator when the voltage of the first conductive element is less than the threshold voltage.
  • the threshold voltage is defined by a transition voltage of an inverter coupled to the first conductive element, the inverter to activate the oscillator when the voltage of the first conductive element is greater than the threshold voltage and to deactivate the oscillator when the voltage of the first conductive element is less than the threshold voltage.
  • Example 23 may include the method of any one of the examples 17-20, further comprising recalibrating one or more operational inputs for the die based on the integrity of dielectric isolation.
  • Example 24 may include the method of any one of the examples 17-20, wherein the DUT is a transistor, and wherein the first conductive element is a first contact of the transistor and the second conductive element is a second contact of the transistor.
  • Example 25 may include a method of determining integrity of dielectric isolation within a die, comprising applying an initial voltage to a device under test (DUT) of the die, the initial voltage applied to a first conductive element of the DUT, coupling a second conductive element of the DUT to ground, the second conductive element isolated from the first conductive element by a dielectric material, reapplying the initial voltage to the first conductive element when a voltage of the first conductive element discharges below a threshold voltage, determining a frequency of the initial voltage being reapplied to the first conductive element, and determining the integrity of dielectric isolation between the first conductive element and the second conductive element based on the frequency.
  • DUT device under test
  • Example 26 may include the method of example 25, further comprising decoupling the second conductive element from ground while reapplying the initial voltage to the first conductive element, and recoupling the second conductive element to ground in response to completion of the reapplying the initial voltage to the first conductive element.
  • Example 27 may include the method of example 25, wherein applying the initial voltage to the first conductive element includes activating a transistor coupled to the first conductive element to couple the first conductive element to a power supply that supplies the initial voltage to the first conductive element and charges a capacitor coupled to the first conductive element to the initial voltage, and deactivating the transistor to decouple the first conductive element from the power supply.
  • Example 28 may include the method of example 25, wherein reapplying the initial voltage to the first conductive element includes activating a transistor coupled to the first conductive element in response to the voltage of the first conductive element discharging below the threshold voltage, activation of the transistor to cause the first conductive element to be coupled to a power supply that supplies the initial voltage to the first conductive element and charges a capacitor coupled to the first conductive element to the initial voltage, and deactivating the transistor to decouple the first conductive element from the power supply.
  • Example 29 may include the method of any one of the examples 27 and 28, wherein the transistor is a first transistor, and wherein coupling the second conductive element of the DUT to ground includes activating a second transistor coupled to the second conductive element to couple the second conductive element to ground.
  • Example 30 may include the method of example 29, wherein the second transistor is activated at substantially a same time as the first transistor is deactivated.
  • Example 31 may include the method of any one of the examples 25-28, wherein determining the frequency of the initial voltage being reapplied includes counting, by a counter, a number of reapplications of the initial voltage to the first conductive element for a time period, and determining the frequency based on the number of reapplications of the initial voltage and the time period.
  • Example 32 may include the method of example 31, wherein the threshold voltage is defined by transition voltages of inverters coupled to the first conductive element, the inverters to cause the counter to increment a count of the number of reapplications in response to the voltage of the first conductive element discharging below the threshold voltage.
  • the threshold voltage is defined by transition voltages of inverters coupled to the first conductive element, the inverters to cause the counter to increment a count of the number of reapplications in response to the voltage of the first conductive element discharging below the threshold voltage.
  • Example 33 may include the method of any one of the examples 25-28, further comprising recalibrating operational inputs for the die based on the integrity of the dielectric isolation.
  • Example 34 may include the method of any one of the examples 25-28, wherein the DUT is a transistor, and wherein the first conductive element is a first contact of the transistor and the second conductive element is a second contact of the transistor.
  • Example 35 may include a die, comprising a first transistor coupled to a first conductive element of the die, the first transistor to couple the first conductive element to a power supply when the first transistor is activated, the power supply to apply an initial voltage to the first conductive element when the power supply is coupled to the first conductive element, a capacitor coupled to the first conductive element, the capacitor to be charged by the power supply when the power supply is coupled to the first conductive element, a second transistor coupled to a second conductive element of the die, the second conductive element dielectrically isolated from the first conductive element, the second transistor to couple the second conductive element to ground when activated, and measurement circuitry to measure one or more discharge characteristics of the first conductive element and to determine integrity of dielectric isolation between the first conductive element and the second conductive element based on the one or more discharge characteristics.
  • Example 36 may include the die of example 35, wherein the first transistor is a p- channel metal-oxide semiconductor field-effect transistor (MOSFET) and the second transistor is a n-channel MOSFET, wherein a gate of the first transistor and a gate of the second transistor are coupled to a single input.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • Example 37 may include the die of any one of the examples 35 and 36, wherein the measurement circuitry includes an oscillator to output an oscillating signal when a voltage of the first conductive element is greater than a threshold voltage, the oscillating signal having oscillations at a constant frequency, and a counter coupled to the oscillator, the counter to count a number of the oscillations, wherein the one or more discharge characteristics include the number of oscillations.
  • the measurement circuitry includes an oscillator to output an oscillating signal when a voltage of the first conductive element is greater than a threshold voltage, the oscillating signal having oscillations at a constant frequency, and a counter coupled to the oscillator, the counter to count a number of the oscillations, wherein the one or more discharge characteristics include the number of oscillations.
  • Example 38 may include The die of example 37, wherein the measurement circuitry further includes an inverter coupled to the first conductive element, wherein a transition voltage of the inverter defines the threshold voltage, and a NOR gate having input terminals coupled to the inverter and an enable input, wherein an output terminal of the NOR gate is coupled to the oscillator, and wherein the NOR gate is to cause the oscillator to output the oscillating signal when the voltage of the conductive element is greater than the threshold voltage and the external input is a logical low.
  • the measurement circuitry further includes an inverter coupled to the first conductive element, wherein a transition voltage of the inverter defines the threshold voltage, and a NOR gate having input terminals coupled to the inverter and an enable input, wherein an output terminal of the NOR gate is coupled to the oscillator, and wherein the NOR gate is to cause the oscillator to output the oscillating signal when the voltage of the conductive element is greater than the threshold voltage and the external input is a logical low.
  • Example 39 may include the die of any one of the examples 35 and 36, wherein the measurement circuitry includes a first inverter, an input of the first inverter coupled to the first conductive element, and a second inverter, an input of the second inverter coupled to an output of the first inverter and an output of the second inverter coupled to the first transistor and the second transistor, the second inverter to control activation of the first transistor and the second transistor, and a voltage at the output of the second inverter to oscillate at a frequency based on a voltage of the first conductive element, wherein the one or more discharge characteristics include the frequency.
  • the measurement circuitry includes a first inverter, an input of the first inverter coupled to the first conductive element, and a second inverter, an input of the second inverter coupled to an output of the first inverter and an output of the second inverter coupled to the first transistor and the second transistor, the second inverter to control activation of the first transistor and the second transistor, and a voltage at the output
  • Example 40 may include the die of example 39, wherein the measurement circuitry further includes a counter to count a number of voltage oscillations at the output of the second inverter over a time period, the measurement circuitry to determine the frequency based on the number of voltage oscillations and the time period.
  • Example 41 may include a computer device, comprising a circuit board, one or more processors mounted to the circuit board, and one or more memory devices mounted to the circuit board, the one or more memory devices having instructions stored thereon, wherein the instructions, in response to execution by the one or more processors, cause the one or more processors to: initiate a dielectric isolation test for a dielectric material that isolates a first conductive element from a second conductive element within a die, the die located within the computer device and the dielectric isolation test to return a dielectric health indicator for the dielectric material, compare the dielectric health indicator with at least one prior dielectric health indicator obtained via at least one prior dielectric isolation test performed on the dielectric material, the at least one prior health indicator stored on the one or more memory devices, and determine whether to initiate a corrective action based on the comparison of the dielectric health indicator with the at least one prior dielectric heath indicator.
  • a computer device comprising a circuit board, one or more processors mounted to the circuit board, and one or more memory devices mounted to the circuit board
  • Example 42 may include the computer device of example 41, wherein to determine whether to initiate the corrective action includes to identify an entry in a lookup table corresponding to a result of the comparison of the dielectric health indicator with the at least one prior dielectric health indicator, the lookup table stored on the one or more memory devices, and determine whether the corrective action is to be initiated based on the entry.
  • Example 43 may include the computer device of any one of the examples 41 and
  • instructions in response to execution by the one or more processors, further cause the one or more processors to initiate the corrective action in response to determining that the corrective action is to be initiated.
  • Example 44 may include the computer device of example 43, wherein the corrective action includes decreasing an output voltage of a low-dropout regulator associated with the die.
  • Example 45 may include the computer device of example 43, wherein the corrective action includes decreasing an output frequency of a phase lock loop associated with the die.
  • Example 46 may include the computer device of any one of the examples 41 and 42, wherein the die is one of the one or more processors.
  • Example 47 may include the computer device of any one of the examples 41 and 42, wherein to initiate the dielectric isolation test includes to activate a first transistor that is coupled to the first conductive element to couple the first conductive element to a power source, the power source to apply an initial voltage to the first conductive element and charge a capacitor coupled to the first conductive element to the initial voltage when the first transistor is activated, deactivate the first transistor to decouple the first conductive element from the power source in response to the capacitor being charged to the initial voltage, and activate a second transistor that is coupled to the second conductive element to couple the second conductive element to ground in response to the first transistor being deactivated.
  • Example 48 may include the computer device of example 47, wherein the dielectric health indicator includes a frequency of oscillations produced by a series of inverters coupled to the first conductive element, the series of inverters to output the oscillations as a voltage of the first conductive element oscillates, wherein the series of inverters are to cause the first transistor to be reactivated when the voltage of the first conductive element is less than a threshold voltage and the first transistor to be deactivated in response to the capacitor being charged to the initial voltage.
  • the dielectric health indicator includes a frequency of oscillations produced by a series of inverters coupled to the first conductive element, the series of inverters to output the oscillations as a voltage of the first conductive element oscillates, wherein the series of inverters are to cause the first transistor to be reactivated when the voltage of the first conductive element is less than a threshold voltage and the first transistor to be deactivated in response to the capacitor being charged to the initial voltage.
  • Example 49 may include the computer device of any one of the examples 41 and
  • the dielectric health indicator includes a number of oscillations within an oscillation signal output by an oscillator that is coupled to the first conductive element via an inverter and a NOR gate, the oscillator to output the oscillations on the oscillation signal when a voltage of the first conductive element is greater than a threshold voltage and to cease output of the oscillations on the oscillation signal when the voltage of the first conductive element is less than or equal to the threshold voltage, and wherein the instructions further cause the one or more processors to count the number of the oscillations on the oscillation signal and return the number of the oscillations.
  • Example 50 may include the computer device of any one of the examples 41 and

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  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne des appareils, des systèmes et des procédés permettant de tester une isolation diélectrique. Un boîtier de semi-conducteur peut comprendre un dispositif à l'essai (DUT). Le DUT peut posséder un premier élément conducteur et un second élément conducteur, le premier élément conducteur étant isolé du second élément conducteur par un matériau diélectrique. Le boîtier de semi-conducteur peut en outre comprendre des circuits de mesure couplés au DUT. Le circuit de mesure peut appliquer une tension initiale au DUT, la tension initiale appliquée au premier élément conducteur et peut coupler le second élément conducteur à la terre. Le circuit de mesure peut en outre déterminer une période de temps de décharge concernant une décharge du premier élément conducteur à une tension de seuil à partir de la tension initiale, et déterminer une intégrité d'isolation diélectrique entre le premier élément conducteur et le second élément conducteur en fonction de la période de décharge.
PCT/US2016/069350 2016-12-29 2016-12-29 Détermination d'intégrité d'isolation sur une puce WO2018125173A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
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US11450613B2 (en) * 2018-03-23 2022-09-20 Intel Corporation Integrated circuit package with test circuitry for testing a channel between dies
CN120263148A (zh) * 2025-06-05 2025-07-04 湖南融创微电子股份有限公司 三模抗辐照时钟电路
EP4617688A1 (fr) * 2024-03-15 2025-09-17 Nxp B.V. Circuit de détermination de la dégradation

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US5039941A (en) * 1990-07-27 1991-08-13 Intel Corporation Voltage threshold measuring circuit
US20090256202A1 (en) * 2008-04-14 2009-10-15 Abou-Khalil Michel J Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures
US20100164530A1 (en) * 2008-12-31 2010-07-01 Jan Hoentschel Adjusting configuration of a multiple gate transistor by controlling individual fins
US20110168995A1 (en) * 2007-06-29 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits
US20150123702A1 (en) * 2013-11-04 2015-05-07 Marvell World Trade Ltd. Method and Apparatus for Authenticating a Semiconductor Die

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Publication number Priority date Publication date Assignee Title
US5039941A (en) * 1990-07-27 1991-08-13 Intel Corporation Voltage threshold measuring circuit
US20110168995A1 (en) * 2007-06-29 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits
US20090256202A1 (en) * 2008-04-14 2009-10-15 Abou-Khalil Michel J Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures
US20100164530A1 (en) * 2008-12-31 2010-07-01 Jan Hoentschel Adjusting configuration of a multiple gate transistor by controlling individual fins
US20150123702A1 (en) * 2013-11-04 2015-05-07 Marvell World Trade Ltd. Method and Apparatus for Authenticating a Semiconductor Die

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11450613B2 (en) * 2018-03-23 2022-09-20 Intel Corporation Integrated circuit package with test circuitry for testing a channel between dies
EP4617688A1 (fr) * 2024-03-15 2025-09-17 Nxp B.V. Circuit de détermination de la dégradation
CN120263148A (zh) * 2025-06-05 2025-07-04 湖南融创微电子股份有限公司 三模抗辐照时钟电路

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