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WO2018133768A1 - Structure de conditionnement et procédé de conditionnement pour puce de reconnaissance d'empreintes digitales - Google Patents

Structure de conditionnement et procédé de conditionnement pour puce de reconnaissance d'empreintes digitales Download PDF

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Publication number
WO2018133768A1
WO2018133768A1 PCT/CN2018/072799 CN2018072799W WO2018133768A1 WO 2018133768 A1 WO2018133768 A1 WO 2018133768A1 CN 2018072799 W CN2018072799 W CN 2018072799W WO 2018133768 A1 WO2018133768 A1 WO 2018133768A1
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WO
WIPO (PCT)
Prior art keywords
fingerprint identification
pad
identification chip
cover
layer
Prior art date
Application number
PCT/CN2018/072799
Other languages
English (en)
Chinese (zh)
Inventor
王之奇
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710034991.9A external-priority patent/CN107046008A/zh
Priority claimed from CN201710083787.6A external-priority patent/CN106684052A/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Publication of WO2018133768A1 publication Critical patent/WO2018133768A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a package structure and a packaging method of a fingerprint identification chip.
  • fingerprint recognition technology Because fingerprints are unique and invariant, fingerprint recognition technology has many advantages such as good security, high reliability and simple use. Therefore, fingerprint recognition technology has become the mainstream technology for identity verification of various electronic devices.
  • a capacitive fingerprint recognition chip and an optical fingerprint recognition chip are two types of fingerprint recognition chips commonly used in existing electronic devices, and collect fingerprint information of users through a large number of pixel points (pixels) in the fingerprint recognition area, each The pixel is used as a detection point.
  • pixel points pixels
  • the fingerprint type fingerprint identification chip performs fingerprint recognition
  • the distance between the ridge line of the fingerprint and the valley line to the fingerprint identification chip is different, so that the detection capacitance formed by the two is different from the fingerprint identification chip, and different regions of the finger are collected through each pixel point.
  • the capacitance value is converted into an electrical signal, and the fingerprint information can be obtained according to the electrical signal converted by all the pixel points; when the optical fingerprint identification chip performs fingerprint recognition, the light is irradiated to the fingerprint surface of the user and reflected by the fingerprint surface to the pixel point.
  • the pixel converts the optical signal of the fingerprint into an electrical signal, and the fingerprint information can be obtained according to the electrical signal converted by all the pixels.
  • the semiconductor cover covering the first surface of the fingerprint identification chip, the semiconductor cover has a plurality of through holes, each of the through holes corresponding to one pixel, and the bottom of the through hole exposes the pixel.
  • the method further includes: a backplane fixed to the fingerprint identification chip;
  • the backplane is disposed on the second surface of the fingerprint identification chip; the backplane includes a first metal wiring layer and a second pad electrically connected to the first metal wiring layer; the first soldering The disk is electrically connected to the second pad.
  • the second surface of the fingerprint identification chip is provided with a via hole for exposing the first pad
  • the via sidewall and the second surface are covered with an insulating layer; the insulating layer surface is provided with a second metal wiring layer, the second metal wiring layer covering the insulating layer and the bottom of the via hole, And electrically connected to the first pad; the second surface is provided with a solder bump, and the solder bump is electrically connected to the second metal wiring layer.
  • a conductive plug is disposed in the via hole, and one end of the conductive plug is electrically connected to the first pad, and the other end of the conductive plug is higher than a second surface of the fingerprint identification chip.
  • the first pad and the second pad are electrically connected by a metal line.
  • the semiconductor cover covers all of the pixel points and exposes all of the first pads
  • the first pad and the second pad are electrically connected by a conductive film layer at least partially covering the first pad and at least partially covering the second pad.
  • the semiconductor cover plate includes a first region facing the sensing region and a second region facing the non-sensing region;
  • the second region is provided with a first recess for exposing the first pad.
  • the first surface is quadrangular, having opposite first sides and second sides;
  • the sensing area is located in the quadrilateral
  • the fingerprint identification chip has a plurality of the first pads, and the plurality of first pads are divided into two groups, and the first group of the first pads are disposed on the sensing area and the first side a second set of the first pads is disposed between the sensing area and the second side;
  • the first groove corresponding to the first group of the first pads has a spacing from the first side, corresponding to the first groove and the second side of the second group of the first pads The sides have a spacing;
  • the first groove corresponding to the first group of the first pads exposes the first side, and the first groove corresponding to the second group of the first pads Exposing the second side;
  • the first recess includes: a second recess located in a surface of the semiconductor cover facing away from the side of the fingerprint identification chip, the second recess having a depth smaller than the semiconductor a thickness of the cover; a plurality of openings in the second recess corresponding to the first pads, the openings for exposing the corresponding first pads.
  • the semiconductor cover is a single crystal silicon cover, or a polysilicon cover, or an amorphous silicon cover, or a silicon germanium cover, or a silicon carbide cover.
  • the fingerprint identification chip and the semiconductor cover are fixed by an adhesive.
  • the fingerprint identification chip is a fingerprint recognition chip of a silicon substrate
  • the semiconductor cover plate and the fingerprint identification chip are fixed by gold-silicon eutectic and mutual fusion bonding.
  • the metal layer comprises a stacked titanium layer, a platinum layer and a gold layer;
  • the titanium layer, the platinum layer and the gold layer are sequentially formed on the surface of the semiconductor cover or the surface of the fingerprint recognition chip by a sputtering process.
  • the semiconductor cover plate and the fingerprint identification chip have a laminated photoresist layer and an adhesive layer;
  • the semiconductor cover plate is fixed on the fingerprint chip by the adhesive layer;
  • the photoresist layer surrounds all of the pixel points.
  • the thickness of the semiconductor cover plate ranges from 200 ⁇ m to 300 ⁇ m, inclusive.
  • the fingerprint identification chip is an optical fingerprint identification chip.
  • the invention also provides a method for packaging a fingerprint identification chip, the packaging method comprising:
  • the cover plate is divided into a plurality of semiconductor cover plates that are fixed to the fingerprint identification chip one by one; the semiconductor cover plate has a plurality of through holes, and the bottom of the through holes exposes the pixels .
  • the through holes are formed on the cover plate in one-to-one correspondence with the pixel points.
  • the through hole is formed on the cap plate by a laser drilling process or a deep silicon etching process.
  • the first surface of the fingerprint identification chip includes a sensing area and a non-sensing area surrounding the sensing area; the pixel is disposed in the sensing area; and the non-sensing area is provided a first pad electrically connected to the pixel, the first pad being for electrical connection with an external circuit.
  • the packaging method further includes: providing a backplane, the backplane comprising a first metal wiring layer and a second electrically connected to the first metal wiring layer Pad
  • the first pad is electrically connected to the second pad.
  • the method further includes:
  • a solder bump electrically connected to the second metal wiring layer is formed.
  • the method further includes:
  • the semiconductor cover covers all of the pixel points and exposes all of the first pads
  • the fixing the fingerprint identification chip to the backboard includes:
  • the first surface in a direction perpendicular to the fingerprint identification chip, is quadrilateral, having opposite first sides and second sides;
  • the fingerprint identification chip has a plurality of the first pads, and the plurality of first pads are divided into two groups, and the first group of the first pads are disposed on the sensing area and the first side a second set of the first pads is disposed between the sensing area and the second side;
  • the first groove corresponding to the first group of the first pads has a spacing from the first side, corresponding to the first groove of the second group of the first pads Having a spacing from the second side;
  • the first groove corresponding to the first group of the first pads exposes the first side, and the first groove corresponding to the second group of the first pads Exposing the second side;
  • first direction is perpendicular to the first side and the second side.
  • the semiconductor cover covers all of the pixel points of the corresponding fingerprint identification chip, and exposes or covers all of the first pads of the corresponding fingerprint identification chip;
  • Covering the cover plate on the first surface of the wafer includes: fixing the cover plate on the surface of the wafer by an adhesive.
  • the covering the cover on the first surface of the wafer comprises:
  • the titanium layer, the platinum layer, and the gold layer are sequentially formed on the surface of the semiconductor cover or the surface of the fingerprint recognition chip by a sputtering process.
  • the covering the first surface of the first surface of the wafer comprises:
  • the semiconductor cover plate is fixed on the fingerprint chip by the adhesive layer;
  • the photoresist layer surrounds all of the pixel points.
  • the fingerprint identification chip is an optical fingerprint recognition chip.
  • a semiconductor cover is disposed on the first surface of the fingerprint identification chip, and the semiconductor cover has a plurality of pixels corresponding to the fingerprint identification chip.
  • Point-to-one corresponding through holes for exposing the pixel points the semiconductor cover plate has a lower dielectric constant, which can reduce the crosstalk problem between adjacent pixel points, and improve the accuracy of fingerprint recognition .
  • the semiconductor cover is a non-transparent material, and the area of the through hole is transparent. Since the through hole has a one-to-one correspondence with the pixel, when the optical fingerprint chip is used, the fingerprint of the preset area can only be collected through the corresponding via for one pixel. The information avoids mutual crosstalk between different pixel points corresponding to the preset area, thereby avoiding distortion of the fingerprint image and further improving the accuracy of fingerprint recognition.
  • the cross-talk problem can be avoided, and the cover plate of the package structure can have greater mechanical strength.
  • the semiconductor cover plate is not affected by the semiconductor cover.
  • the deformation of the thickness caused by the pressing of the finger does not affect the accuracy of the fingerprint recognition; on the other hand, the substrate of the fingerprint identification chip can be further thinned, while ensuring the mechanical strength of the package structure and avoiding crosstalk problems. Yes, the fingerprint recognition chip has a thin thickness.
  • FIG. 1b is a schematic structural diagram of another package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • Figure 1e is a top view of Figure 1d;
  • Figure 1g is a top view of Figure 1f;
  • FIG. 2 is a schematic diagram of a package structure of another fingerprint identification chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a package structure of another fingerprint identification chip according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a package structure of another fingerprint identification chip according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a package structure of another fingerprint identification chip according to an embodiment of the present invention.
  • 11a-18 are schematic flowcharts of a method for forming a back surface structure of a wafer according to an embodiment of the present invention.
  • FIG. 19 is a schematic flow chart of another method for forming a back surface structure of a wafer according to an embodiment of the present invention.
  • FIG. 24 to FIG. 27 are schematic diagrams showing the process of simultaneously forming a through hole and a first recess on a semiconductor cover according to an embodiment of the present invention.
  • the package structure includes a fingerprint identification chip 11 and a semiconductor cover covering the first surface 111 of the fingerprint identification chip 11. 12.
  • the periphery of the semiconductor cover 12 may be fixed to a region opposing the first surface 111.
  • the fingerprint identification chip 11 includes an opposite first surface 111 and a second surface 112 having a plurality of pixel points 13 for acquiring fingerprint information.
  • the semiconductor cover 12 has a plurality of through holes 14. The bottom of the through hole 14 exposes the pixel point 13. The bottom of the through hole 14 is an opening of the through hole 14 close to the pixel point 13.
  • the through holes 14 may be provided in one-to-one correspondence with the pixel points 13 for exposing the corresponding pixel points 13.
  • the semiconductor cover 12 has a lower dielectric constant and can reduce crosstalk problems between adjacent pixel points 13.
  • the projection of the through hole 14 at the first surface 111 overlaps at least the projected portion of the corresponding pixel point 13 at the first surface 111.
  • the projection of the through hole 14 at the first surface 111 may be set to completely cover the projection of the corresponding pixel point 13 on the first surface 111.
  • the projection of the through hole 14 at the first surface 111 can be set to completely coincide with the projection of the corresponding pixel 13 at the first surface 111.
  • the first surface 111 includes a sensing area a and a non-sensing area b surrounding the sensing area a.
  • the pixel 13 is disposed in the sensing area a; the non-sensing area b is provided with a first pad 15 electrically connected to the pixel 13 for electrically connecting to an external circuit. If the fingerprint identification chip 11 is a capacitive fingerprint recognition chip, when the fingerprint recognition is performed, the pixel 13 detects the capacitance value, converts the capacitance value into an electrical signal, and the external circuit can acquire the fingerprint information according to the electrical signal to perform identity recognition.
  • the through hole is used to expose the pixel, and the semiconductor cover has a lower dielectric constant, which can reduce crosstalk between adjacent pixels and improve the accuracy of fingerprint recognition.
  • the fingerprint recognition chip 11 is an optical fingerprint identification chip
  • the pixel point 13 collects the fingerprint information of the acquisition preset area opposite to the via hole 14 through the corresponding via hole 14 . Since each pixel point 13 collects the fingerprint information of the opposite collection area through the corresponding via hole 14, the mutual crosstalk between the different pixel points corresponding to the preset area is avoided, thereby avoiding the distortion of the fingerprint image, and further improving the fingerprint recognition. The accuracy.
  • the semiconductor cover 12 is a cover plate made of a semiconductor material such as a single crystal silicon cover, or a polysilicon cover, or an amorphous silicon cover, or a silicon germanium cover, or a silicon carbide cover.
  • the semiconductor cover 12 of the semiconductor material has a lower dielectric constant, which can effectively reduce the crosstalk problem of adjacent pixel points 13.
  • the semiconductor cover 12 prepared by the semiconductor material generally has a Mohs hardness of 10 or more.
  • the hardness is high, the mechanical strength is large, and the thickness deformation is not generated when the finger is pressed, and the accuracy of the fingerprint recognition is not affected, and the semiconductor cover 12 can be multiplexed into the cover of the package structure, and the cover plate does not need to be separately provided, thereby reducing Thickness and production cost.
  • the thickness of the semiconductor cover 12 ranges from 200 ⁇ m to 300 ⁇ m, inclusive.
  • a semiconductor cover 12 having a relatively large thickness such as a semiconductor cover 12 having a thickness of 300 ⁇ m, may be employed.
  • the cover plate of the package structure can have greater mechanical strength, and when the fingerprint is recognized, the semiconductor cover 12 is not deformed by the thickness of the finger, thereby ensuring fingerprint recognition.
  • the substrate of the fingerprint identification chip 11 can be further thinned to make the fingerprint identification chip 11 have a thin thickness while ensuring the mechanical strength of the package structure and avoiding the crosstalk problem.
  • the through hole 14 may be provided in the shape of a circular through hole or a square through hole or a triangular through hole. Specifically, the shape of the through hole 14 may be the same as that of the top and the bottom, or the same square hole with the top and the bottom, or the same triangular hole with the top and the bottom, or the same polygon with the top and bottom of the other structure.
  • the bottom of the through hole 14 is an opening of the through hole 14 close to the pixel point 13
  • the top of the through hole 14 is an opening of the through hole 14 away from the pixel point 13.
  • the through hole 14 in the shape of a circular hole whose top and bottom are different, or a square hole which is different from the top and the bottom, or a triangular hole which is different from the top and the bottom, or a polygon which is different from the top and bottom of other structures.
  • the top of the through hole 14 is larger than the bottom of the through hole 14.
  • the bottom of the through hole 14 is an opening of the through hole 14 near the pixel point 13
  • the top of the through hole 14 is an opening of the through hole 14 away from the pixel point 13.
  • the fingerprint identification chip 11 and the semiconductor cover 12 are fixed by an adhesive 16.
  • the fingerprint identification chip 11 and the semiconductor cover 12 are fixed by a soldering process.
  • the surfaces of the fingerprint identification chip 11 opposite to the semiconductor cover 12 are respectively provided with fixing pads for soldering, and the fixing pads on the surfaces of the two are fixed and fixed by a soldering process, so that the semiconductor cover 12 is fixed on the fingerprint.
  • the chip 11 is identified.
  • the semiconductor cover 12 and the fingerprint identification chip 11 are fixed by gold-silicon eutectic and mutual fusion bonding.
  • the two can be fixed in the following two ways.
  • One way is to provide the fingerprint recognition chip 11 as a fingerprint recognition chip of a silicon substrate, and to provide the semiconductor cover 12 with a metal layer facing the periphery of the surface of the fingerprint recognition chip 11.
  • the region of the metal layer opposite to the silicon substrate is fixed by gold-silicon eutectic and mutual fusion bonding, thereby further fixing the semiconductor cover 12 to the fingerprint recognition chip 11.
  • the metal layer includes a stacked titanium layer, a platinum layer, and a gold layer; wherein a titanium layer, a platinum layer, and a gold layer are sequentially formed on the surface of the semiconductor cover 12 by a sputtering process.
  • the semiconductor cover 12 is a silicon cover, and to provide a metal layer in a region where the first surface 111 corresponds to the periphery of the semiconductor cover 12.
  • the metal layer and the periphery of the silicon cap are fixed by gold-silicon eutectic and mutual fusion, thereby fixing the semiconductor cover 12 to the fingerprint recognition chip 11.
  • the metal layer includes a titanium layer, a platinum layer, and a gold layer which are laminated. Among them, a titanium layer, a platinum layer, and a gold layer are sequentially formed on the first surface 111 by a sputtering process.
  • the adhesive layer of a large thickness is required, which may cause the adhesive 16 to overflow and contaminate other components of the package structure.
  • the photoresist may be simultaneously used.
  • the adhesive fixing fingerprint identification chip 11 and the semiconductor cover 12 are provided.
  • the package structure can be as shown in FIG. 1b or FIG. 1c.
  • the fingerprint identification chip 11 and the semiconductor cover 12 have a laminated adhesive layer 16 and a photoresist layer 161.
  • the semiconductor cover 12 is fixed on the fingerprint chip 11 by the adhesive layer 16. Wherein the photoresist layer 161 surrounds all of the pixel points.
  • FIG. 1b is a schematic structural diagram of a package structure of another fingerprint identification chip according to an embodiment of the present invention.
  • the semiconductor cover 12 is disposed on the surface of the fingerprint identification chip 11 with a photoresist layer 161; the surface of the photoresist layer 161 has an adhesive layer 16; and the semiconductor cover 12 is fixed on the fingerprint chip 11 by the adhesive layer 16. on.
  • the vertical projection of the photoresist layer 161 on the fingerprint recognition chip 11 surrounds all the pixel points 13.
  • FIG. 1c is a schematic structural diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the first surface 111 of the fingerprint identification chip 11 is provided with a photoresist layer 161 surrounding all the pixel points 13; the surface of the photoresist layer 161 has an adhesive layer 16; and the semiconductor cover 12 is fixed by the adhesive layer 16.
  • the fingerprint chip 11 is provided with a photoresist layer 161 surrounding all the pixel points 13; the surface of the photoresist layer 161 has an adhesive layer 16; and the semiconductor cover 12 is fixed by the adhesive layer 16.
  • the fingerprint chip 11 is provided with a photoresist layer 161 surrounding all the pixel points 13; the surface of the photoresist layer 161 has an adhesive layer 16; and the semiconductor cover 12 is fixed by the adhesive layer 16.
  • the fingerprint chip 11 is provided with a photoresist layer 161 surrounding all the pixel points 13; the surface of the photoresist layer 161 has an adhesive layer 16; and the semiconductor cover 12 is fixed by the
  • the semiconductor cover 12 includes a first region that faces the sensing region a and a second region that faces the non-sensing region b.
  • the second region is provided with a first recess for exposing the first pad to facilitate circuit interconnection with an external circuit.
  • the package structure may be as shown in FIGS. 1d-1i.
  • FIG. 1d - FIG. 1i only the semiconductor cover 12 and the fingerprint identification chip 11 are fixed in the manner shown in FIG. 1c, and the semiconductor cover 12 and the fingerprint identification chip 11 can be fixed in the manner shown in FIG. 1a or Figure 1b shows the way.
  • FIG. 1d is a schematic structural diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention
  • FIG. 1e is a top view of FIG. 1d.
  • the first surface 111 is quadrangular, having an opposite first side 1000 and a second side 1001; the sensing area a is located in the Inside the quadrilateral.
  • the sensing area a and the non-sensing area b are only for the convenience of describing the relative positions of the structure names, and may or may not have visible boundary lines therebetween.
  • the first pads 15 of each group can be made in one or more columns.
  • the fingerprint identification chip has a plurality of the first pads 15, and the plurality of the first pads 15 are divided into two groups, and the first group of the first pads 15 are disposed in the sensing area a and the Between the first side 1000, a second set of the first pads 15 is disposed between the sensing area a and the second side 1001.
  • the shape of the pixel 13 and the through hole 14 can be set according to requirements, and is not limited to the illustrated manner.
  • the shape of the top view of the pixel 13 may be a circle or a square.
  • the shape of the through hole 14 may be a circular hole or a square, and the shape of the pixel 13 and the through hole 14 may be the same or different.
  • the first groove A1 corresponding to the first group of the first pads 15 has a spacing from the first side 1000, corresponding to the second
  • the first groove A1 of the first pad 15 has a spacing from the second side 1001; wherein the first direction is perpendicular to the first side 1000 and the second side 1001.
  • FIG. 1f is a schematic structural diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention
  • FIG. 1g is a top view of FIG. 1f.
  • the first recess A1 corresponding to the first group of the first pads 15 exposes the first side 1000, corresponding to the first recess of the second group of the first pads 15.
  • the groove A1 exposes the second side 1001.
  • FIG. 1h is a schematic structural diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention
  • FIG. 1i is a top view of FIG. 1h.
  • the first recess A1 includes: a second recess A2 located in a surface of the semiconductor cover 12 facing away from the fingerprint identification chip 11 , the second recess A2 having a depth smaller than the semiconductor cover
  • the thickness of the plate 12 is a plurality of openings A3 located in the second recess A2 corresponding to the first pads 15 for exposing the corresponding first pads 15.
  • the outer edge of the second recess A2 may coincide with the corresponding side of the semiconductor cover 12 or be located within the side.
  • FIG. 2 is a schematic diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the package structure further includes: a back fixed with the fingerprint identification chip 11 on the basis of the package structure shown in FIG. Board 22.
  • the back plate 22 is disposed on the second surface 112 of the fingerprint identification chip 11; the back plate 22 includes a first metal wiring layer; and a second pad 21 electrically connected to the first metal wiring layer.
  • the first pad 15 is electrically connected 21 to the second pad.
  • the first metal wiring layer is electrically connected to an external circuit.
  • the first metal wiring layer is not shown in FIG. 2, and the second pad 21 electrically connected to the first metal wiring layer is shown.
  • the semiconductor cover 12 covers all of the pixel points 13. According to the electrical connection of the first pad 15 and the second pad 21, the semiconductor cover 12 is disposed to cover all of the first pads 15 or to expose all of the first pads 15.
  • the backboard 22 includes: a PCB substrate, a glass substrate, a metal substrate, a cover semiconductor substrate, and a polymer flexible substrate.
  • the fingerprint identification chip 11 and the backing plate 22 are bonded and fixed by the adhesive layer 23.
  • the fingerprint identification chip 11 and the back plate 22 can also be fixed by soldering.
  • the surface of the fingerprint identification chip 11 and the surface of the back plate 22 both have a fixed pad formed by a sputtering process, and the fingerprint is processed by a soldering process.
  • the fixing pads of the identification chip 11 are soldered and fixed to the fixing pads of the back plate 22.
  • the fingerprint identification chip 11 and the back plate 22 may also be fixed by gold-silicon eutectic, mutual fusion bonding, gold-silicon eutectic, mutual fusion bonding and the fingerprint identification chip 11 and the semiconductor cover 12
  • gold-silicon eutectic and the mutual fusion bonding The principle of the gold-silicon eutectic and the mutual fusion bonding is the same, and the above description can be referred to, and details are not described herein again.
  • the package structure further includes a third pad 26 disposed on the backplane 22 for electrically connecting to an external circuit.
  • the third pad 26 can be electrically connected to an external circuit by using a flexible wiring board (FPC) or a bonding metal wire.
  • FPC flexible wiring board
  • the second surface 112 is provided with a via 24 for exposing the first pad 15 on the first surface 111.
  • the sidewall of the via 24 is provided with an insulating layer, which is not shown in FIG.
  • a conductive plug 25 is disposed in the via hole 24, and one end of the conductive plug 25 is electrically connected to the first pad 15 and the other end is higher than the second surface 112 to be electrically connected to the second pad 21.
  • the other end of the conductive plug 25 has solder and can be soldered to the second pad 21.
  • the semiconductor cover 12 and the fingerprint identification chip 11 may have the same opposing area. At this time, the semiconductor cap 12 covers all of the pixel dots 13 and all of the first pads 15.
  • the second pad 21 is disposed opposite to the first pad 15, and the surface of the second pad 21 opposite to the first pad 15 may be the same or different.
  • FIG. 3 is a schematic diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the package structure is different from that of FIG. 2 in that the semiconductor cover 12 covers all The pixel 13 is exposed and all of the first pads 15 are exposed.
  • a relatively small size semiconductor cover 12 can be employed with respect to the embodiment shown in FIG.
  • FIG. 4 is a schematic diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the package structure is different from the manner shown in FIG.
  • the pad 15 and the second pad 21 are electrically connected by a metal line 31.
  • the metal wires 31 may be soldered and fixed to the first pads 15 and the second pads 21, respectively, by a soldering process.
  • the semiconductor cover 12 is provided to cover all the pixel dots 13, and all the first pads 15 are exposed.
  • FIG. 5 is a schematic diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the package structure is different from the manner shown in FIG.
  • the pad 15 and the second pad 21 are electrically connected by a conductive paste 32.
  • the conductive paste 32 at least partially covers the first pad 15 and at least partially covers the second pad 21.
  • the semiconductor cover 12 is disposed to cover all the pixel dots 13, and all the first pads 15 are exposed.
  • FIG. 6 is a schematic diagram of a package structure of a fingerprint identification chip according to an embodiment of the present invention.
  • the package structure is different from the manner shown in FIG.
  • the pad 15 and the second pad 21 are electrically connected through the conductive film layer 33.
  • the conductive film layer 33 at least partially covers the first pad 15 and at least partially covers the second pad 21.
  • the conductive film layer 33 can be formed by an evaporation process.
  • the semiconductor cover 12 is provided to cover all the pixel dots 13, and all the first pads 15 are exposed.
  • the structure of the fingerprint identification chip 11 is not limited to the illustrated structure of the above embodiments.
  • the first surface 111 may be provided with a boss structure, and the sensing may be provided.
  • the area a is located on the surface of the boss structure, and the non-sensing area b is located in the recess area around the boss structure.
  • the package structure provided by the example of the present invention can also be packaged by a TSV (Through-Silicon-Via) process. At this time, the structure of the chip is as shown in FIG. 7.
  • FIG. 7 shows another package of the fingerprint identification chip provided by the embodiment of the present invention. Schematic.
  • the difference from the above-described package structure is that the structure of the back surface of the fingerprint recognition chip 11 is different, and the connection mode of the back plate 22 and the fingerprint recognition chip 11 is different.
  • the second surface 112 is provided with a via 74 for exposing the first pad 15.
  • the second surface 112 is provided with a third recess 77, and a via 74 is disposed in the third recess 77, and the via 74 exposes the first pad 15.
  • the sidewalls of the vias 74 and the second surface 112 are provided with an insulating layer 76.
  • the surface of the insulating layer 76 is further provided with a second metal wiring layer 71 covering the insulating layer 76 and the bottom of the via hole 74, and is electrically connected to the first pad 15 through the via hole 74.
  • the bottom of the via 74 is the opening of the via 74 toward the first pad 15.
  • the semiconductor cover 12 covers all of the pixel points 13 and may expose all of the first pads 15 or cover all of the first pads 15.
  • the second surface is provided with solder bumps 73, and the solder bumps 73 are electrically connected to the second metal wiring layer 71.
  • the solder bumps 73 and the second pads 21 are electrically connected.
  • the surface of the second metal wiring layer 71 is provided with a solder resist layer 72, and the solder resist layer 72 is provided with an opening for providing the solder bumps 73.
  • a glue layer 75 is disposed between the backboard 22 and the fingerprint identification chip 11 to fix the backplane 22 on the fingerprint identification chip 11.
  • the backplane 22 and the fingerprint identification chip 11 may also be fixed by gold-silicon eutectic, mutual fusion bonding, or by a soldering process, and the specific implementation manner and the semiconductor cover 12 and the fingerprint identification chip 11 described above.
  • the gold-silicon eutectic, mutual fusion bonding and fixing methods are the same, and the above description may be referred to, and details are not described herein again.
  • the fingerprint identification chip 11 in the embodiment of the present invention may preferably adopt an optical fingerprint recognition chip.
  • the through holes 14 in the semiconductor cover 12 can control the incident angle of light incident on the respective pixel points 13, avoiding the crosstalk problem of the pixel points 13.
  • the semiconductor cover 12 is disposed on the first surface 111 of the fingerprint identification chip 11, and the semiconductor cover 12 has a plurality of pixel points 13 and 13 of the fingerprint identification chip 11. Corresponding through holes 14 , the through holes 14 are used to expose the pixel points 13 , which can reduce the crosstalk problem between adjacent pixel points 13 and improve the accuracy of fingerprint recognition.
  • the present invention can multiplex the semiconductor cap 12 as a prior art solution for avoiding crosstalk by using a photoresist layer having via holes.
  • the cover of the package structure eliminates the need to separately provide a cover plate, which reduces the manufacturing cost and the thickness of the package structure.
  • the finger pressing the photoresist layer may cause the photoresist layer to be The thickness is deformed, and even if a photoresist layer having a large thickness is provided on the first surface, the substrate of the fingerprint identification chip 11 cannot be further thinned due to its small mechanical strength.
  • the cover plate of the package structure can have greater mechanical strength, and when the fingerprint is recognized, the semiconductor cover 12 is not pressed by the finger.
  • the deformation of the thickness does not affect the accuracy of the fingerprint recognition; on the other hand, the substrate of the fingerprint identification chip 11 can be further thinned, while ensuring the mechanical strength of the package structure and avoiding the crosstalk problem.
  • the fingerprint recognition chip 11 has a relatively thin thickness.
  • FIG. 8 to FIG. 10 A schematic flowchart of a method for packaging a fingerprint identification chip, the package method comprising:
  • Step S11 As shown in FIGS. 8 and 9, a wafer 100 is provided.
  • the wafer 100 has opposing first and second surfaces 111 and 112.
  • the wafer 100 includes a plurality of arrays of fingerprint identification chips 11 arranged.
  • Each adjacent fingerprint identification chip 11 has a plurality of pixel points 13 for acquiring fingerprint information.
  • the pixel 13 is located on the first surface 111.
  • a cutting channel 120 is provided between adjacent fingerprint identification chips 11 to facilitate the cutting process in a subsequent cutting process.
  • the first surface 111 includes a sensing area a and a non-sensing area b surrounding the sensing area a.
  • the pixel 13 is disposed in the sensing area a.
  • the first pad 15 is provided in the non-sensing area b.
  • the first pad 15 is electrically connected to the pixel point 13.
  • the first pad 15 is for electrical connection with an external circuit.
  • the cutting channel 120 between two adjacent fingerprint identification chips 11 is only a blank area reserved for cutting between the two fingerprint identification chips 11, and the cutting channel 120 and the fingerprints on both sides are required. There is no actual boundary line between the identification chips 11.
  • Step S12 As shown in FIG. 10, the cover 200 is covered on the first surface 111 of the wafer 100.
  • the cover 200 is disposed toward the pixel point 13.
  • the cover plate 200 may be disposed to face the surface of the wafer 100 with no gap contact with the pixel dots 13. It may be disposed in a direction perpendicular to the cap plate 200, and the cap plate 200 is disposed opposite to the wafer 100, that is, the surfaces opposite thereto.
  • the cover 200 is divided into a plurality of semiconductor cover plates 12 after cutting.
  • the semiconductor cover 12 covers all the pixel points 13 corresponding to the fingerprint identification chip 11, and the semiconductor cover 12 is exposed or covered according to the electrical connection manner of the first pad 15 and the second pad 21. Corresponding fingerprints identify all of the first pads of the chip 11.
  • the cover 200 is fixed to the surface of the wafer 100 by the adhesive 16.
  • the package structure is shown in Figure 1a.
  • the cover plate 200 is fixed on the surface of the wafer 100 by the adhesive 16
  • the adhesive layer of the predetermined pattern is formed on the wafer 100 toward the first surface 111 of the cover 200, and the adhesive layer has a plurality of the fingerprint identification chips 11 A corresponding opening. All of the pixel points 13 of the fingerprint recognition chip 11 are located in the corresponding openings.
  • a predetermined pattern of adhesive layers is formed on the surface of the cover 200 toward the wafer, and the adhesive layer has a plurality of openings corresponding to the fingerprint identification chip 11 in one-to-one correspondence.
  • the vertical projection of any opening in the wafer 100 covers all of the pixel points 13 of the corresponding fingerprinting chip 11.
  • the glue 16 can be formed by screen printing. According to the electrical connection manner of the first pad 15 and the second pad 21, the opening on the adhesive layer is disposed to cover all the first pads 15 corresponding to the fingerprint identification chip 11 or all the first pads corresponding to the fingerprint identification chip 11 are exposed. Disk 15.
  • the cover 200 may also be fixed on the surface of the wafer 100 by a soldering process.
  • the cover 200 is fixed on the surface of the wafer 100 by a soldering process
  • the wafer 100 and the cover 200 each have a fixed pad, and the solder pad 100 is fixed to the surface of the wafer 200, and the cover is fixed on the surface of the wafer 100.
  • Board 200
  • a metal layer may be disposed between the semiconductor cover 12 and the fingerprint identification chip 11; the semiconductor cover 12 and the fingerprint identification chip 11 are fixed by gold-silicon eutectic and mutual fusion. .
  • the two can be fixed in the following two ways.
  • One way is to form a metal layer on the periphery of the cover plate 200 toward the area of each fingerprint identification chip 11; at a set temperature and pressure, the gold-silicon eutectic, mutual fusion, so that the metal layer and the fingerprint identification chip 11
  • the cover 200 is fixed to the surface of the wafer 100 in combination with fixing. After cutting.
  • Each fingerprint identification chip 11 and the corresponding semiconductor cover 12 are fixed to each other by a gold-silicon eutectic and inter-melting process.
  • the wafer 100 is a silicon substrate to realize gold-silicon eutectic and mutual fusion bonding.
  • a titanium layer, a platinum layer, and a gold layer are sequentially formed on the surface of the region of the cover plate 200 facing each of the fingerprint recognition chips 11 by a sputtering process.
  • Another way is to form a metal layer in a region of the first surface 111 of each fingerprint identification chip 11 corresponding to the periphery of the semiconductor cover 12; at a set temperature and pressure, the gold-silicon eutectic, mutual fusion, so that The metal layer is fixedly coupled to the cover 200 to fix the cover 200 to the surface of the wafer 100. Again, after cutting.
  • Each fingerprint identification chip 11 and the corresponding semiconductor cover 12 are fixed to each other by a gold-silicon eutectic and inter-melting process.
  • the cover 200 is a silicon wafer to realize gold-silicon eutectic and mutual fusion bonding.
  • a titanium layer, a platinum layer, and a gold layer are sequentially formed on the first surface 111 of each of the fingerprint recognition chips 11 by a sputtering process.
  • a photoresist layer of a predetermined pattern structure may be formed on the surface of the wafer 100 corresponding to the cover plate 200; the photoresist layer has a plurality of openings corresponding to the fingerprint identification chip 11 in one-to-one correspondence, and the opening is on the wafer 100.
  • the upper vertical projection covers all the pixel points 13 corresponding to the fingerprint recognition chip 11; the top surface of the photoresist layer is coated with adhesive, and the cover 200 is fixed on the wafer 100 by adhesive.
  • a photoresist layer of a predetermined pattern structure may be formed on the surface of the wafer 100 corresponding to the cover plate 200; the photoresist layer has a plurality of openings corresponding to the fingerprint identification chip 11 one by one, and the opening surrounds the corresponding fingerprint recognition All the pixel points 13 of the chip 11 are coated with a glue on the top surface of the photoresist layer, and the cover plate 200 is fixed on the wafer 100 by the adhesive.
  • the package structure is shown in Figure 1c.
  • a photoresist layer of a predetermined pattern structure may be formed by screen printing, and the photoresist layer is cured by an exposure and development process.
  • the adhesive may be formed on the top surface of the photoresist layer of the predetermined pattern structure by a screen printing or spin coating process.
  • the surface of the wafer 200 facing away from the cover 200 can be thinned, so that the cut fingerprint identification chip 11 has a thinner thickness. thickness. That is, the second surface 112 of all the fingerprint recognition chips 11 can be thinned to reduce the thickness of the fingerprint recognition chip 11.
  • the surface of the wafer 100 facing away from the side of the first cover 200 may be thinned by a mechanical grinding process.
  • the thinning process of the wafer 100 can be performed when the back surface structure of the wafer 100 is formed, and can be designed according to the process flow, and the specific timing of the thinning process is not specifically limited herein.
  • covering the cover plate 200 on the first surface 111 of the wafer 100 includes: forming a pixel point on the cover plate 200 after the first surface 111 of the wafer 100 covers the cover plate 200 and before the cutting process 13 through one corresponding through hole 14.
  • the cover plate 200 may be formed in one-to-one correspondence with the pixel points 13 before the cover plate 200 is covered on the first surface 111 of the wafer 100 .
  • Through hole 14 In this time, in order to avoid contamination of the pixel 13 when the back surface structure of the wafer 100 is formed on the side of the wafer 100 facing away from the cover 200, the via hole 14 may be filled with photoresist or the cover plate 200 may be separated from the crystal.
  • a shielding plate is provided on one side of the circle 100. If the photoresist is filled in the via hole 14 and the back surface structure is formed, the photoresist is removed and subjected to a subsequent dicing process. If a shielding plate is disposed on a side of the cover 200 facing away from the wafer 100, after forming the back structure of the package structure, after the cutting process is performed, the shielding plate is removed.
  • the through holes 14 may be formed by a laser drilling process or a deep silicon etching process.
  • Step S13 dividing the wafer 100 and the cover 200 by a dicing process to form a package structure of a plurality of fingerprint identification chips.
  • the cutting is performed in the direction of the cutting channel 120 to form a package structure of the plurality of fingerprint recognition chips 11.
  • the cover 200 is divided into a plurality of semiconductor cover plates 12 that are fixed to the fingerprint identification chip 11 one by one; each of the semiconductor cover 12 has a plurality of through holes 14 and a relatively fixed semiconductor cover 12 and In the fingerprint recognition chip 11, the through holes 14 are disposed opposite to the pixel points 13 one by one, and the bottom of the through holes 14 exposes the pixel points 13.
  • a photoresist layer is generally used as a dielectric layer with a low dielectric constant to reduce crosstalk between adjacent pixel points. Therefore, after a conventional packaging process forms a photoresist layer on the surface of the wafer, it is required to be in the photoresist.
  • a protective substrate having a large mechanical strength and a good flatness is pre-fixed on the layer to facilitate forming a back plate on the other side of the wafer, so that the first pad is connected to an external circuit, and then the protective substrate is removed.
  • the cover 200 can be multiplexed as a protective substrate, and the wafer 100 to which the cover 200 is fixed is inverted.
  • the wafer 100 faces upward, and a back plate is formed on the side of the wafer 100 facing away from the cover 200.
  • the back plate is cut to form a back plate of the package structure, so that the first pad 15 is electrically connected to an external circuit. It can be seen that the cutting method provided by the embodiment of the present invention can multiplex the cover plate 200 to protect the substrate, and the process is simple and the manufacturing cost is low.
  • the packaging method further includes: providing a backplane, the backplane includes a first metal wiring layer and a second pad electrically connected to the first metal wiring layer; fixing the fingerprint identification chip on the backplane, and fingerprint recognition The second surface of the chip is attached to the backplane; the first pad is electrically connected to the second pad.
  • FIG. 11 is a schematic diagram of a method for forming a back surface structure of a wafer according to an embodiment of the present invention. The method includes:
  • Step S20 As shown in FIG. 11a, a shielding plate 400 is disposed on the top of the through hole 14 or a photoresist is filled in the through hole 14.
  • a shielding plate 400 is provided on the top of the through hole 14 as an example for illustration.
  • a shielding plate 400 is disposed on the top of the through hole 14.
  • the wafer 100 may be caused.
  • the semiconductor cover 12 can be disposed to cover all the pixel points 13 of the corresponding fingerprint identification chip 11 according to the electrical connection manner, and expose or cover all the first pads 15 of the corresponding fingerprint identification chip 11.
  • Step S21 As shown in Fig. 11b and Fig. 12, a via hole 74 is formed on the second surface, and the via hole 74 is used to expose the first pad 15.
  • the wafer 100 is inverted, so that the cover 200 is located under the wafer 100, and the surface of the wafer 100 facing away from the pixel 13 is thinned. Processing to reduce the thickness of the fingerprint recognition chip 11 and to facilitate the formation of vias 74.
  • a third recess 77 is formed on the surface of the wafer 100 facing away from the cover 200.
  • the depth of the third recess 77 is smaller than the thickness of the wafer 100 to facilitate the formation of the via 74.
  • the third groove 77 is disposed opposite to the non-sensing zone. After the first etching process, the third grooves 77 are located on both sides of the second face 112 of the fingerprint identification chip 11. Only two adjacent fingerprint identification chips 11 are shown in Fig. 11b with a dicing trench 120 therebetween.
  • Step S24 As shown in FIGS. 15 to 16, a solder bump 73 electrically connected to the second metal wiring layer 71 is formed.
  • the shutter 400 is removed to facilitate cutting. After being cut along the dicing trench 120, a plurality of package structures as shown in FIG. 18 are formed. After the backplane is fixed on the second surface of the wafer, the package structure formed is as shown in FIG.
  • FIG. 19 to FIG. 23 are another forming wafer back surface structure according to an embodiment of the present invention. Schematic diagram of the method, the method comprising:
  • Step S30 As shown in FIG. 11a, a shielding plate 400 is disposed on the top of the through hole 14 of the cover 200 or a photoresist is filled in the through hole 14.
  • step S20 The same as the above step S20, reference may be made to the above step S20, and details are not described herein again.
  • Step S31 As shown in FIG. 19, a via hole 24 corresponding to the first pad 15 is formed on the second surface 112 of the fingerprint recognition chip 11, and the via hole 24 is used to expose the first pad 15.
  • Step S32 As shown in FIG. 20, an insulating layer covering the second surface 112 of the wafer 100 and the sidewalls of the via 500 is formed. In FIG. 20, the insulating layer is not shown. A conductive plug 25 is formed in the via hole 24, and one end of the conductive plug 25 is electrically connected to the first pad 15, and the other end of the conductive plug 25 is higher than the second surface 112 of the fingerprint identification chip 11.
  • the conductive plug 25 has solder for electrically connecting to the second pad. That is, the conductive plug 25 has solder at one end facing away from the first pad 15, and solder is not shown in FIG.
  • the shutter 400 is removed to facilitate cutting.
  • a plurality of package structures as shown in FIG. 22 are formed.
  • the package structure formed is as shown in FIG.
  • the diced semiconductor cover 12 covers all of the pixel points 13 corresponding to the fingerprint identification chip 11 and all of the first pads 15.
  • the fixed binding position of the fingerprint identification chip 11 and the corresponding semiconductor cover 12 can be set, so that the cut semiconductor cover 12 covers all the pixel points 13 corresponding to the fingerprint identification chip 11 and exposes the corresponding fingerprint identification chip 11 All of the first pads 15 are as shown in FIG. After the backing plate 22 is fixed on the second surface of the wafer, the package structure formed is as shown in FIG.
  • the surface of the wafer 100 facing away from the cover 200 is fixed by the adhesive layer 23.
  • the backplane 300 and the wafer 100 can also be fixed by soldering, or gold-silicon eutectic, mutual fusion, and the principle is the same as that of the semiconductor cover 12 and the fingerprint identification chip 11, as described above, and no longer Narration.
  • the semiconductor cover 12 includes a first region facing the sensing region and a second region facing the non-sensing region;
  • the first recess A1 of the first pad 15 is exposed to facilitate circuit interconnection with an external circuit, and the package structure formed may be as shown in FIGS. 1d-1i.
  • the first recess A1 may be formed while forming the through hole 14 to simplify the manufacturing process and reduce the manufacturing cost.
  • the first surface is quadrilateral having opposite first sides and second sides; the sensing area is located within the quadrilateral; the fingerprint
  • the identification chip has a plurality of the first pads 15, and the plurality of the first pads 15 are divided into two groups, and the first group of the first pads 15 are disposed on the sensing area and the first side A second set of the first pads 15 is disposed between the sensing area and the second side.
  • the first groove A1 is formed while forming the through hole 14, and in this case, in the first direction, corresponding to the first group
  • the first groove A1 of the first pad 15 has a spacing from the first side
  • the first groove corresponding to the second group of the first pad 15 has a spacing from the second side .
  • the first groove A1 is formed simultaneously with the formation of the through hole 14, and in this case, corresponding to the first group in the first direction.
  • the first groove A1 of the first pad 15 exposes the first side
  • the first groove A1 corresponding to the second group of the first pad 15 exposes the second side.
  • the first groove A1 is formed while forming the through hole 14.
  • the first groove A1 includes a second recess A2 located in a surface of the semiconductor cover 12 facing away from the side of the fingerprint identification chip 11, the second recess A2 having a depth smaller than a thickness of the semiconductor cover 12; A plurality of openings A3 corresponding to the first pads 15 in the slot A2, the openings A3 are used to expose the corresponding first pads 15.
  • the etching needs to be performed twice, and the through holes 14 are formed in two steps so as to simultaneously form the first grooves A1 and the through holes 14.
  • the wafer 100 is fixed to the cover 200, the wafer 100 is thinned away from the other side of the cover 200, and then cut.
  • the process forms a plurality of package structures, each package structure having a relatively fixed fingerprint identification chip 11 and a semiconductor cover plate.
  • the side of the fingerprint recognition chip 11 facing away from the semiconductor cover 12 is fixed to the back plate 22.
  • fixing the fingerprint identification chip 11 to the backboard 22 includes: passing a metal wire (as shown in FIG. 4), or a conductive adhesive (as shown in FIG. 5), or a conductive film layer (as shown in FIG. 6).
  • the first pad 15 and the second pad 21 are electrically connected.
  • the encapsulation method provided by the embodiment of the invention is used for preparing the package structure in the above embodiment, has a simple manufacturing process and low cost, and can form a package structure of a fingerprint identification chip for preventing crosstalk.
  • the cover plate is fixed on one side of the wafer facing the pixel point.
  • the cover plate is used to form a semiconductor cover plate of each package structure for avoiding crosstalk problem
  • the cover plate It can also be used as a protective substrate to form a back structure on the side of the wafer facing away from the pixel, which is convenient for electrical connection with the backplane, without separately providing a protective substrate, reducing the process flow and manufacturing cost.

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Abstract

L'invention concerne une structure de conditionnement et un procédé de conditionnement pour une puce de reconnaissance d'empreintes digitales (11). La structure de conditionnement comprend : une puce de reconnaissance d'empreinte digitale (11), la puce de reconnaissance d'empreinte digitale (11) comprenant une première surface (111) et une seconde surface (112) qui sont opposées l'une à l'autre, et la première surface (111) est pourvue d'une pluralité de points de pixel (13) pour acquérir des informations d'empreintes digitales ; et une carte de recouvrement semi-conductrice (12) recouvrant la première surface (111), la carte de recouvrement semi-conductrice (12) étant pourvue d'une pluralité de trous traversants (14), et les points de pixel (13) étant exposés au niveau des fonds des trous traversants (14). La carte de recouvrement semi-conductrice (12) est disposée sur la première surface (111) de la puce de reconnaissance d'empreintes digitales (11); la carte de recouvrement semi-conductrice (12) est pourvue d'une pluralité de trous traversants (14) correspondant aux points de pixels (13) de la puce de reconnaissance d'empreintes digitales (11) d'une part ; et les trous traversants (14) sont utilisés pour exposer les points de pixel (13), de telle sorte que le problème de diaphonie entre des points de pixel adjacents (13) peut être réduit, ce qui permet d'améliorer la précision de la reconnaissance d'empreintes digitales.
PCT/CN2018/072799 2017-01-17 2018-01-16 Structure de conditionnement et procédé de conditionnement pour puce de reconnaissance d'empreintes digitales WO2018133768A1 (fr)

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CN201710034991.9A CN107046008A (zh) 2017-01-17 2017-01-17 一种指纹识别芯片的封装结构以及封装方法
CN201710034991.9 2017-01-17
CN201720053790 2017-01-17
CN201720141464 2017-02-16
CN201710083787.6 2017-02-16
CN201720141464.3 2017-02-16
CN201710083787.6A CN106684052A (zh) 2017-02-16 2017-02-16 指纹识别芯片封装结构以及封装方法

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