WO2018138829A1 - High frequency branching filter and high frequency circuit using same - Google Patents
High frequency branching filter and high frequency circuit using same Download PDFInfo
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- WO2018138829A1 WO2018138829A1 PCT/JP2017/002728 JP2017002728W WO2018138829A1 WO 2018138829 A1 WO2018138829 A1 WO 2018138829A1 JP 2017002728 W JP2017002728 W JP 2017002728W WO 2018138829 A1 WO2018138829 A1 WO 2018138829A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/213—Frequency-selective devices, e.g. filters combining or separating two or more different frequencies
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- the present invention relates to a high-frequency demultiplexer that demultiplexes radio waves having a plurality of input frequencies, and a high-frequency circuit using the same.
- This high-frequency demultiplexer has a configuration in which band-pass filters having passbands of second, third, and fourth harmonics are connected in parallel.
- a frequency corresponding to the pass frequency band of the band pass filter is output from a separate terminal.
- the conventional high frequency demultiplexer requires a plurality of filters, which increases the size and does not satisfy the demand for miniaturization.
- the present invention has been made to solve such a problem, and an object of the present invention is to provide a high frequency demultiplexer that can be miniaturized.
- the high frequency branching filter according to the present invention includes first to fourth terminals.
- the first terminal is an input terminal
- the second terminal is an isolation terminal
- the third terminal is a 0 ° output terminal
- the fourth terminal is a 90 ° hybrid circuit that has a relationship of being a ⁇ 90 ° output terminal
- the first frequency is a radio wave having a phase delayed by 90 ° relative to the radio wave applied to the first terminal.
- a phase shift circuit for providing the second terminal with a radio wave having a phase advanced by 90 ° relative to the radio wave provided to the first terminal.
- a high frequency duplexer includes a 90 ° hybrid circuit having first and second terminals to which radio waves having a first frequency and a second frequency are input, and a first frequency input to the second terminal.
- the first frequency radio wave is delayed by 90 ° from the first frequency radio wave input to the first terminal, and the second frequency radio wave input to the second terminal is input to the first terminal.
- the phase is 90 degrees ahead of the second frequency radio wave.
- FIG. 1 is a configuration diagram of a high frequency demultiplexer according to the present embodiment.
- the high frequency branching filter according to the present embodiment includes an input terminal 100, a phase shift circuit 3 that equally distributes high frequency power input from the input terminal 100, and provides a phase difference.
- a 90 ° hybrid circuit 2 having fourth terminals 21, 22, 23, and 24 is provided.
- the phase shift circuit 3 equally distributes the high frequency input to the input terminal 100 by the in-phase distributor 31, gives one output to the first terminal 21 of the 90 ° hybrid circuit 2, and supplies the other output to the fundamental wave.
- the terminal 24 is in the relationship of being a ⁇ 90 ° output terminal.
- the 90 ° hybrid circuit 2 is composed of, for example, a Lange coupler.
- the fundamental wave, which is the first frequency and the third harmonic wave, which is the second frequency, input from the input terminal 100 are divided into two at the same amplitude by the in-phase distributor 31 in the phase shift circuit 3.
- One output of the in-phase distributor 31 is input to the first terminal 21 of the 90 ° hybrid circuit 2, and the other output of the in-phase distributor 31 is 90 ° via a transmission line 32 having a fundamental wavelength of 1 ⁇ 4 wavelength.
- the signal is input to the second terminal 22 of the hybrid circuit 2.
- the fundamental wave input to the second terminal 22 of the 90 ° hybrid circuit 2 is 90 ° out of phase with the fundamental wave input to the first terminal 21, and is input to the second terminal 22.
- the third harmonic wave is 90 ° ahead of the third harmonic wave input to the first terminal 21.
- the 90 ° hybrid circuit 2 shifts the high frequency input to the first terminal 21 by ⁇ and outputs it from the third terminal 23, and shifts by ⁇ 90 ° and outputs it from the fourth terminal 24.
- the high frequency input to the second terminal 22 is phase-shifted by ⁇ and output from the fourth terminal 24, and phase-shifted by ⁇ 90 ° and output from the third terminal 23.
- ⁇ is set to 0 °.
- the fundamental wave inputted to the first terminal 21 of the 90 ° hybrid circuit 2 and the fundamental wave delayed by 90 ° inputted to the second terminal 22 are not outputted at the third terminal 23 due to the reverse phase synthesis.
- 4 terminal 24 outputs in-phase synthesis.
- the third harmonic wave input to the first terminal 21 and the third harmonic wave advanced by 90 ° input to the second terminal 22 are not output in the fourth terminal 24 and are not output.
- in-phase synthesis is performed and output. Therefore, the fundamental wave and the third harmonic wave input to the input terminal 100 are demultiplexed and output from the fourth terminal 24 and the third terminal 23, respectively.
- the first frequency is the fundamental wave
- the second frequency is the third harmonic
- the phase shift circuit 3 similarly applies the second frequency to the second terminal 22 of the 90 ° hybrid circuit 2 at other frequencies.
- the phase of the first frequency radio wave input is delayed by 90 ° from the first frequency radio wave input to the first terminal 21 and the phase of the second frequency radio wave input to the second terminal 22 is delayed. Can be demultiplexed by advancing the phase by 90 ° relative to the radio wave of the second frequency input to the first terminal 21.
- the fourth terminal 24 of the 90 ° hybrid circuit 2 is provided with an open stub 40 having a quarter wavelength of the fundamental wave, so that the third harmonic wave demultiplexed at the third terminal 23 is obtained.
- the fundamental wave can be reflected back to the input terminal 100 without affecting the signal.
- the fundamental wave is reflected to the input terminal 100 without affecting the third harmonic wave. Can be returned.
- the loop gain can be improved and the output frequency can be increased. There is an effect that can be.
- the input terminal 100 may be provided with a short stub 41 having a fundamental wavelength of 1 ⁇ 4 wavelength.
- the second harmonic wave can be reflected without affecting the fundamental wave and the third harmonic wave, and the input of the second harmonic wave can be suppressed and separated.
- a high frequency demultiplexer is applied to an oscillator, a fundamental wave, a second harmonic wave, and a third harmonic wave are output from the oscillator.
- the output of the second harmonic wave is unnecessary, this can be suppressed as an input, and emission of unnecessary waves can be suppressed.
- the input terminal 100 may be provided with a short stub 41 and a resistor 42 having a fundamental wave of 1 ⁇ 4 wavelength.
- the resistor 42 is connected to one end of the short stub 41 that opens the fundamental wave.
- the second terminal is an isolation terminal
- the third terminal is a 0 ° output terminal
- the fourth terminal is a -90 ° output terminal
- the 90 ° hybrid circuit and the radio wave applied to the first terminal with respect to the first frequency among the input radio waves.
- a phase shift circuit that applies to the second terminal radio waves that are delayed by 90 ° relative to the second terminal, and applies to the second terminals radio waves that are advanced by 90 ° relative to radio waves that are applied to the first terminal with respect to the second frequency. Therefore, the radio waves of the first frequency and the second frequency can be demultiplexed without using a plurality of filters, and the size can be reduced.
- the first frequency is the fundamental wave
- the second frequency is the third harmonic
- the phase shift circuit converts the fundamental wave and the third harmonic to the first frequency.
- An in-phase distributor that distributes to the terminal and the second terminal at the same phase and with equal amplitude; and an electric length between the in-phase distributor and the first terminal, provided between the in-phase distributor and the second terminal. Since a transmission line having a quarter wavelength longer than the fundamental wave is also provided, the fundamental wave and the third harmonic wave can be demultiplexed and output.
- the fourth terminal is provided with the open stub having a 1 ⁇ 4 wavelength at the first frequency, so that the demultiplexed third harmonic is affected. Instead, the fundamental wave can be reflected back to the input terminal of the high frequency demultiplexer.
- the short stub having a quarter wavelength at the first frequency is provided at the input terminal of the high frequency demultiplexer or the phase shift circuit, the fundamental wave and 3 The second harmonic wave is reflected without affecting the second harmonic wave, and the input of the second harmonic wave can be suppressed and separated.
- the second harmonic wave can be generated without affecting the fundamental wave and the third harmonic wave. It is possible to attenuate and suppress the input of the second harmonic.
- FIG. FIG. 6 is a configuration diagram showing a high frequency amplifier using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the second embodiment.
- the high frequency demultiplexer 1a is the high frequency demultiplexer shown in FIG. 4 of the first embodiment, and the corresponding parts are denoted by the same reference numerals and description thereof is omitted.
- the input terminal 100 in the high frequency demultiplexer 1a is configured to be supplied with the output of the amplifier 5, and the third terminal 23 of the 90 ° hybrid circuit 2 in the high frequency demultiplexer 1a has a third wavelength and a quarter wavelength.
- An open stub 43 is provided.
- the operation of the high frequency demultiplexer 1a is the same as that of the first embodiment.
- the short wave is short-circuited and reflected by the short stub 41 independently of the fundamental wave and the third harmonic wave, and is reflected by the open stub 43 independently of the fundamental wave and the second harmonic wave.
- the third harmonic wave can be reflected and returned to the input terminal 100. Therefore, the phase of the second harmonic can be designed independently from the electrical length from the amplifier 5 to the short stub 41, and the phase of the third harmonic from the electrical length from the amplifier 5 to the open stub 43 can be designed independently.
- the fundamental wave, the second harmonic, and the third harmonic can be designed independently, so that the harmonic processing becomes easy. That is, in the harmonic processing, a fundamental wave, a harmonic wave such as a second harmonic wave and a third harmonic wave are combined to form a desired waveform. At that time, these phase relationships are important. For example, when the fundamental wave and the third harmonic wave are combined in phase, the shape approaches a rectangle. The waveform collapses. Therefore, harmonic processing or waveform formation is facilitated by the fact that the fundamental and harmonic phases can be designed independently.
- an amplifier is connected to the input terminal of the high frequency branching filter or phase shift circuit of the first embodiment, and the third terminal is connected to the second frequency. Since an open stub having a quarter wavelength is provided, harmonic processing can be easily performed, and power consumption of the amplifier can be improved.
- FIG. 7 is a configuration diagram showing a high frequency oscillator using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the third embodiment.
- the high-frequency demultiplexer 1 is the high-frequency demultiplexer shown in FIG. 1.
- the drain terminal of the transistor 60 is connected to the input terminal 100 in the high frequency demultiplexer 1, and the fourth terminal 24 in the high frequency demultiplexer 1 is open.
- the transistor 60 includes a feedback circuit 61 and a feedback circuit 62 at its source terminal and gate terminal, respectively.
- the operation of the high frequency demultiplexer 1 is the same as the operation of the configuration shown in FIG.
- the high frequency demultiplexer 1 shown in FIG. 7 operates as one of the feedback circuits of the oscillator, and the fundamental wave reflected by the fourth terminal 24 of the 90 ° hybrid circuit 2 returns to the input terminal 100, and the transistor 60.
- the fundamental wave is fed back in series.
- the high frequency (initially noise) input to the gate terminal of the transistor 60 is amplified by the transistor 60 and output to the drain terminal, and the high frequency reflected by the drain terminal side circuit (here, the high frequency demultiplexer 1) is the transistor 60.
- the signal is input to the feedback circuit 61 through the drain-source and reflected from the source. Further, the signal is input to the feedback circuit 62 via the gate and source of the transistor 60, reflected, and fed back to the gate terminal of the transistor 60 so as to be in phase. This high frequency becomes the oscillation frequency.
- the gain obtained by making a circuit of the transistor and the feedback circuit connected to each terminal of the transistor is positive, and the larger one is easier to oscillate.
- the high-frequency oscillator shown in FIG. 7 feeds back the fundamental wave for performing the oscillation operation to the transistor 60 without outputting it to an external load. Therefore, the loop gain of the oscillator is improved and the oscillator can easily perform the oscillation operation. Further, the third harmonic wave obtained by the oscillation operation is output from the third terminal 23 of the 90 ° hybrid circuit 2.
- the high frequency demultiplexer is connected to the drain terminal as one of the feedback circuits, but the high frequency demultiplexer may be provided at the gate terminal or the source terminal.
- the input terminal of the high frequency duplexer of the first embodiment configured as a feedback circuit is connected to at least one of the transistor terminals, and the oscillation Since the operation is performed, the fundamental wave that performs the oscillating operation by the high frequency demultiplexer can be fed back and the third harmonic wave that is the harmonic thereof can be output, so that the oscillating operation can be easily realized.
- phase noise can be improved because transistors and resonators having better performance can be used than when the oscillator is configured with a frequency corresponding to the third harmonic directly. This is because the loss is lower and the parasitic component is smaller when the low frequency is handled.
- the fundamental wave is applied to the input terminal of the high frequency demultiplexer without affecting the demultiplexed third harmonic. It can be reflected back.
- FIG. 8 is a configuration diagram showing a PLL synthesizer using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the fourth embodiment.
- the high-frequency demultiplexer 1 is the high-frequency demultiplexer shown in FIG.
- a voltage controlled oscillator (VCO) 70 of a phase locked loop (PLL) is connected to the input terminal 100 in the high frequency demultiplexer 1, and the fundamental wave output from the fourth terminal 24 of the 90 ° hybrid circuit 2 is a PLL circuit unit. 71, and the output of the PLL circuit unit 71 is given to the voltage controlled oscillator 70 to perform negative feedback control.
- VCO voltage controlled oscillator
- PLL phase locked loop
- the PLL circuit unit 71 is a circuit configured by a phase comparator, a reference oscillator, a loop filter, a prescaler, and the like, and the voltage controlled oscillator 70 and the PLL circuit unit 71 configure a known phase synchronization circuit. .
- the operation of the high frequency demultiplexer 1 is the same as that of the first embodiment.
- the voltage controlled oscillator 70 is a circuit whose oscillation frequency changes by controlling the voltage, and performs an oscillation operation with a fundamental wave.
- the fundamental wave output from the voltage controlled oscillator 70 is output from the fourth terminal 24 of the 90 ° hybrid circuit 2 via the high frequency duplexer 1.
- the fundamental wave output from the fourth terminal 24 is phase-compared with the reference frequency output from the reference oscillator in the PLL circuit unit 71, and the PLL circuit unit 71 supplies the voltage controlled oscillator 70 with a voltage corresponding to the phase error.
- the voltage controlled oscillator 70 corrects the oscillation frequency according to the applied voltage.
- the third harmonic generated by this oscillation operation is not output from the fourth terminal 24 of the 90 ° hybrid circuit 2 but is output from the third terminal 23.
- the output of the fourth terminal of the high frequency demultiplexer of the first embodiment includes the phase synchronization circuit that inputs the radio wave for phase comparison with the reference frequency, Since the output of the voltage controlled oscillator of the phase locked loop is connected to the input terminal of the high frequency demultiplexer, the following effects are obtained.
- a fundamental wave that oscillates with a high frequency demultiplexer connected to the output of the oscillator and its third harmonic are demultiplexed, the fundamental wave is input to the phase locked loop, and the third harmonic is output to the outside
- the prescaler used in the phase synchronization circuit can be reduced or the frequency dividing number can be reduced, and the PLL synthesizer can be downsized and the phase noise can be improved.
- the effect of improving the phase noise of the oscillator is achieved.
- the high frequency demultiplexer and the high frequency circuit according to the present invention relate to a configuration of a high frequency demultiplexer that demultiplexes radio waves having a plurality of input frequencies and a high frequency circuit using the high frequency demultiplexer. It is suitable for use in high frequency amplifiers, high frequency oscillators, PLL synthesizers and the like.
- 1, 1a High frequency demultiplexer 2 90 ° hybrid circuit, 3 phase shift circuit, 5 amplifier, 21 1st terminal, 22 2nd terminal, 23 3rd terminal, 24 4th terminal, 31 in-phase distributor , 32 transmission lines, 40, 43 open stubs, 41 short stubs, 42 resistors, 60 transistors, 61, 62 feedback circuits, 70 voltage controlled oscillators, 71 PLL circuit units, 100 input terminals.
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Abstract
Description
本発明は、複数の入力周波数の電波を分波する高周波分波器及びこれを用いた高周波回路に関するものである。 The present invention relates to a high-frequency demultiplexer that demultiplexes radio waves having a plurality of input frequencies, and a high-frequency circuit using the same.
従来の高周波分波器として、複数のバンドパスフィルタを用いた構成があった(例えば、特許文献1参照)。この高周波分波器は、2倍波、3倍波、4倍波を通過帯域とするバンドパスフィルタを並列接続した構成である。この高周波分波器では、高調波を含む電波が高周波分波器に入力されると別々の端子からバンドパスフィルタの通過周波数帯域に応じた周波数が出力される。 As a conventional high frequency demultiplexer, there is a configuration using a plurality of band pass filters (see, for example, Patent Document 1). This high-frequency demultiplexer has a configuration in which band-pass filters having passbands of second, third, and fourth harmonics are connected in parallel. In this high frequency demultiplexer, when a radio wave including harmonics is input to the high frequency demultiplexer, a frequency corresponding to the pass frequency band of the band pass filter is output from a separate terminal.
しかしながら、従来の高周波分波器では、複数のフィルタを要するため、サイズが大きくなってしまい、小型化の要求を満たすものではなかった。 However, the conventional high frequency demultiplexer requires a plurality of filters, which increases the size and does not satisfy the demand for miniaturization.
この発明は、かかる問題を解決するためになされたもので、小型化を図ることのできる高周波分波器を提供することを目的とする。 The present invention has been made to solve such a problem, and an object of the present invention is to provide a high frequency demultiplexer that can be miniaturized.
この発明に係る高周波分波器は、第1から第4の端子を備え、第1の端子を入力端子としたとき、第2の端子はアイソレーション端子、第3の端子は0°出力端子、第4の端子は-90°出力端子となる関係にある90°ハイブリッド回路と、入力される電波のうち、第1の周波数に関して、第1の端子に与える電波よりも90°位相を遅らせた電波を第2の端子に与え、第2の周波数に関して、第1の端子に与える電波よりも90°位相を進めた電波を第2の端子に与える移相回路とを備えたものである。 The high frequency branching filter according to the present invention includes first to fourth terminals. When the first terminal is an input terminal, the second terminal is an isolation terminal, the third terminal is a 0 ° output terminal, The fourth terminal is a 90 ° hybrid circuit that has a relationship of being a −90 ° output terminal, and of the input radio waves, the first frequency is a radio wave having a phase delayed by 90 ° relative to the radio wave applied to the first terminal. Is provided to the second terminal, and with respect to the second frequency, there is provided a phase shift circuit for providing the second terminal with a radio wave having a phase advanced by 90 ° relative to the radio wave provided to the first terminal.
この発明に係る高周波分波器は、第1の周波数と第2の周波数の電波が入力される第1及び第2の端子を有する90°ハイブリッド回路を備え、第2の端子に入力される第1の周波数の電波は第1の端子に入力される第1の周波数の電波よりも90°位相が遅れ、第2の端子に入力される第2の周波数の電波は第1の端子に入力される第2の周波数の電波よりも90°位相が進んでいるようにしたものである。これにより、複数のフィルタを用いずに第1の周波数と第2の周波数の電波を分波することができ、小型化を図ることができる。 A high frequency duplexer according to the present invention includes a 90 ° hybrid circuit having first and second terminals to which radio waves having a first frequency and a second frequency are input, and a first frequency input to the second terminal. The first frequency radio wave is delayed by 90 ° from the first frequency radio wave input to the first terminal, and the second frequency radio wave input to the second terminal is input to the first terminal. The phase is 90 degrees ahead of the second frequency radio wave. Thereby, the radio waves of the first frequency and the second frequency can be demultiplexed without using a plurality of filters, and the size can be reduced.
以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態1.
図1は、本実施の形態による高周波分波器の構成図である。
本実施の形態による高周波分波器は、図1に示すように、入力端子100と、入力端子100から入力された高周波電力を等分配し、位相差を与える移相回路3と、第1から第4の端子21、22、23、24を備えた90°ハイブリッド回路2を備える。移相回路3は、入力端子100に入力された高周波を同相分配器31にて等分配して、一方の出力を90°ハイブリッド回路2の第1の端子21に与え、他方の出力を基本波で1/4波長となる伝送線路32を介して90°ハイブリッド回路2の第2の端子22に与える。ここで、90°ハイブリッド回路2の第1の端子21を入力(IN)端子としたとき、第2の端子22はアイソレーション(ISO)端子、第3の端子23は0°出力端子、第4の端子24は-90°出力端子となる関係にある。90°ハイブリッド回路2としては、例えば、ランゲカプラなどで構成する。
Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a configuration diagram of a high frequency demultiplexer according to the present embodiment.
As shown in FIG. 1, the high frequency branching filter according to the present embodiment includes an
次に、実施の形態1の高周波分波器の動作を説明する。
入力端子100から入力された第1の周波数である基本波と第2の周波数である3倍波は移相回路3において同相分配器31によりそれぞれ等振幅で2分配される。同相分配器31の一方の出力は90°ハイブリッド回路2の第1の端子21に入力され、同相分配器31の他方の出力は基本波で1/4波長となる伝送線路32を介して90°ハイブリッド回路2の第2の端子22に入力される。このとき、90°ハイブリッド回路2の第2の端子22に入力される基本波は第1の端子21に入力される基本波よりも90°位相が遅れており、第2の端子22に入力される3倍波は第1の端子21に入力される3倍波よりも90°位相が進んでいる。
Next, the operation of the high frequency demultiplexer according to the first embodiment will be described.
The fundamental wave, which is the first frequency and the third harmonic wave, which is the second frequency, input from the
90°ハイブリッド回路2は、第1の端子21に入力された高周波をθ移相して第3の端子23から出力し、θ-90°移相して第4の端子24から出力する。同様に、第2の端子22に入力された高周波をθ移相して第4の端子24から出力し、θ-90°移相して第3の端子23から出力する。ここでは説明を簡単にするため、θを0°とする。
The 90 °
90°ハイブリッド回路2の第1の端子21に入力された基本波と第2の端子22に入力された90°遅れた基本波は、第3の端子23では逆相合成となり出力されず、第4の端子24では同相合成となり出力されることになる。一方、第1の端子21に入力された3倍波と第2の端子22に入力された90°進んだ3倍波は、第4の端子24では逆相合成となり出力されず、第3の端子23では同相合成となり、出力されることになる。
従って、入力端子100に入力された基本波と3倍波は分波され、それぞれ第4の端子24と第3の端子23から出力される。
The fundamental wave inputted to the
Therefore, the fundamental wave and the third harmonic wave input to the
上記の説明では、第1の周波数を基本波、第2の周波数を3倍波としたが、他の周波数でも同様に、移相回路3によって、90°ハイブリッド回路2の第2の端子22に入力される第1の周波数の電波の位相を第1の端子21に入力される第1の周波数の電波よりも90°遅らせ、第2の端子22に入力される第2の周波数の電波の位相を第1の端子21に入力される第2の周波数の電波よりも90°位相を進ませることで、分波することができる。
In the above description, the first frequency is the fundamental wave, and the second frequency is the third harmonic. However, the
また、図2に示すように、90°ハイブリッド回路2の第4の端子24に基本波で1/4波長のオープンスタブ40を備えることで、第3の端子23で分波された3倍波には影響を与えずに、基本波を入力端子100に反射して戻すことができる。また、図3に示すように、90°ハイブリッド回路2の第4の端子24を開放としても同様に分波された3倍波には影響を与えずに、基本波を入力端子100に反射して戻すことができる。このように、基本波を入力端子100に反射して戻すことにより、例えば高周波分波器を発振器の帰還回路の一つとして適用した場合、ループ利得の向上が図れ、出力周波数の高周波化を図ることができるという効果がある。
Further, as shown in FIG. 2, the
さらに、図4に示すように、入力端子100に基本波で1/4波長のショートスタブ41を備えても良い。これにより、基本波と3倍波に影響を与えずに2倍波を反射させ、2倍波の入力を抑え、分離することができる。例えば、高周波分波器を発振器に適用した場合、発振器からは基本波、2倍波及び3倍波が出力される。ここで、基本波と3倍波を取り出したい場合、2倍波の出力は不要であるため、入力としてこれを抑えることができ、不要波の放射を抑えることができる。
Furthermore, as shown in FIG. 4, the
また、図5に示すように、入力端子100に基本波で1/4波長のショートスタブ41と抵抗42を備えても良い。抵抗42は、基本波が開放となるショートスタブ41の一端に接続される。これにより、基本波と3倍波に影響を与えずに2倍波を減衰させ、2倍波の入力を抑えることができ、不要波の放射を抑えることができる。
Further, as shown in FIG. 5, the
以上説明したように、実施の形態1の高周波分波器によれば、第1から第4の端子を備え、第1の端子を入力端子としたとき、第2の端子はアイソレーション端子、第3の端子は0°出力端子、第4の端子は-90°出力端子となる関係にある90°ハイブリッド回路と、入力される電波のうち、第1の周波数に関して、第1の端子に与える電波よりも90°位相を遅らせた電波を第2の端子に与え、第2の周波数に関して、第1の端子に与える電波よりも90°位相を進めた電波を第2の端子に与える移相回路とを備えたので、複数のフィルタを用いずに第1の周波数と第2の周波数の電波を分波することができ、小型化を図ることができる。 As described above, according to the high frequency demultiplexer of the first embodiment, when the first to fourth terminals are provided and the first terminal is an input terminal, the second terminal is an isolation terminal, The third terminal is a 0 ° output terminal, the fourth terminal is a -90 ° output terminal, and the 90 ° hybrid circuit, and the radio wave applied to the first terminal with respect to the first frequency among the input radio waves. A phase shift circuit that applies to the second terminal radio waves that are delayed by 90 ° relative to the second terminal, and applies to the second terminals radio waves that are advanced by 90 ° relative to radio waves that are applied to the first terminal with respect to the second frequency. Therefore, the radio waves of the first frequency and the second frequency can be demultiplexed without using a plurality of filters, and the size can be reduced.
また、実施の形態1の高周波分波器によれば、第1の周波数は基本波、第2の周波数は3倍波であり、移相回路は、基本波及び3倍波を、第1の端子と第2の端子とに同相かつ等振幅で分配する同相分配器と、同相分配器と第2の端子との間に設けられ、同相分配器と第1の端子との間の電気長よりも基本波で1/4波長長い伝送線路とを備えたので、基本波と3倍波の電波を分波して出力することができる。 Further, according to the high frequency demultiplexer of the first embodiment, the first frequency is the fundamental wave, the second frequency is the third harmonic, and the phase shift circuit converts the fundamental wave and the third harmonic to the first frequency. An in-phase distributor that distributes to the terminal and the second terminal at the same phase and with equal amplitude; and an electric length between the in-phase distributor and the first terminal, provided between the in-phase distributor and the second terminal. Since a transmission line having a quarter wavelength longer than the fundamental wave is also provided, the fundamental wave and the third harmonic wave can be demultiplexed and output.
また、実施の形態1の高周波分波器によれば、第4の端子に第1の周波数で1/4波長となるオープンスタブを備えたので、分波された3倍波には影響を与えずに、基本波を当該高周波分波器の入力端子に反射して戻すことができる。 In addition, according to the high frequency demultiplexer of the first embodiment, the fourth terminal is provided with the open stub having a ¼ wavelength at the first frequency, so that the demultiplexed third harmonic is affected. Instead, the fundamental wave can be reflected back to the input terminal of the high frequency demultiplexer.
また、実施の形態1の高周波分波器によれば、当該高周波分波器または移相回路の入力端子に第1の周波数で1/4波長となるショートスタブを備えたので、基本波と3倍波に影響を与えずに2倍波を反射させ、2倍波の入力を抑え、分離することができる。 Further, according to the high frequency demultiplexer of the first embodiment, since the short stub having a quarter wavelength at the first frequency is provided at the input terminal of the high frequency demultiplexer or the phase shift circuit, the fundamental wave and 3 The second harmonic wave is reflected without affecting the second harmonic wave, and the input of the second harmonic wave can be suppressed and separated.
また、実施の形態1の高周波分波器によれば、ショートスタブの第1の周波数で開放となる先端に抵抗を備えたので、基本波と3倍波に影響を与えずに2倍波を減衰させ、2倍波の入力を抑えることができる。 Further, according to the high frequency demultiplexer of the first embodiment, since the resistor is provided at the tip that is open at the first frequency of the short stub, the second harmonic wave can be generated without affecting the fundamental wave and the third harmonic wave. It is possible to attenuate and suppress the input of the second harmonic.
実施の形態2.
図6は、実施の形態2の高周波回路として、実施の形態1の高周波分波器を用いた高周波増幅器を示す構成図である。
図6において、高周波分波器1aは実施の形態1の図4に示す高周波分波器であり、対応する部分に同一符号を付してその説明を省略する。高周波分波器1aにおける入力端子100には増幅器5の出力が与えられるよう構成され、高周波分波器1aにおける90°ハイブリッド回路2の第3の端子23には3倍波で1/4波長のオープンスタブ43を備えている。
FIG. 6 is a configuration diagram showing a high frequency amplifier using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the second embodiment.
In FIG. 6, the
次に、実施の形態2の動作について説明する。
高周波分波器1aの動作は実施の形態1と同様である。ただし、図6に示す高周波分波器1aにおいては、基本波及び3倍波と独立にショートスタブ41で2倍波を短絡して反射させ、基本波及び2倍波と独立にオープンスタブ43により3倍波を反射させて、入力端子100に戻すことができる。このため、増幅器5からショートスタブ41までの電気長で2倍波の位相を、増幅器5からオープンスタブ43までの電気長で3倍波の位相を独立に設計することができる。
Next, the operation of the second embodiment will be described.
The operation of the
このように、実施の形態2の高周波回路では、基本波、2倍波、3倍波の位相を独立して設計できるため、高調波処理が容易となる。すなわち、高調波処理では、基本波と2倍波、3倍波などの高調波を合成し、所望の波形を形成する。そのとき、これらの位相関係が重要である。例えば、基本波と3倍波を同相で合成すると矩形に近づくが、2倍波の位相を設計するときに基本波、3倍波の位相が変化して同相関係から乖離すると良好な合成ができず波形が崩れてしまう。従って、基本波及び高調波の位相を独立に設計できることにより、高調波処理または波形形成が容易となる。 As described above, in the high-frequency circuit of the second embodiment, the fundamental wave, the second harmonic, and the third harmonic can be designed independently, so that the harmonic processing becomes easy. That is, in the harmonic processing, a fundamental wave, a harmonic wave such as a second harmonic wave and a third harmonic wave are combined to form a desired waveform. At that time, these phase relationships are important. For example, when the fundamental wave and the third harmonic wave are combined in phase, the shape approaches a rectangle. The waveform collapses. Therefore, harmonic processing or waveform formation is facilitated by the fact that the fundamental and harmonic phases can be designed independently.
以上説明したように、実施の形態2の高周波回路によれば、実施の形態1の高周波分波器または移相回路の入力端子に増幅器を接続すると共に、第3の端子に第2の周波数で1/4波長となるオープンスタブを備えたので、高調波処理が容易に行え、増幅器の消費電力を改善することができる。 As described above, according to the high frequency circuit of the second embodiment, an amplifier is connected to the input terminal of the high frequency branching filter or phase shift circuit of the first embodiment, and the third terminal is connected to the second frequency. Since an open stub having a quarter wavelength is provided, harmonic processing can be easily performed, and power consumption of the amplifier can be improved.
実施の形態3.
図7は、実施の形態3の高周波回路として、実施の形態1の高周波分波器を用いた高周波発振器を示す構成図である。
図7において、高周波分波器1は図1に示す高周波分波器であり、対応する部分に同一符号を付してその説明を省略する。高周波分波器1における入力端子100にはトランジスタ60のドレイン端子が接続され、高周波分波器1における第4の端子24は開放となっている。トランジスタ60はそのソース端子とゲート端子にそれぞれ帰還回路61と帰還回路62を備えている。
FIG. 7 is a configuration diagram showing a high frequency oscillator using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the third embodiment.
In FIG. 7, the high-
次に、実施の形態3の動作について説明する。
高周波分波器1の動作は実施の形態1の図1に示した構成の動作と同様である。ただし、図7に示す高周波分波器1は、発振器の帰還回路の一つとして動作しており、90°ハイブリッド回路2の第4の端子24で反射した基本波は入力端子100に戻り、トランジスタ60に入力される。実施の形態3の高周波発振器では、基本波を直列帰還している。トランジスタ60のゲート端子に入力される高周波(最初は雑音)はトランジスタ60で増幅されてドレイン端子に出力され、ドレイン端子側回路(ここでは高周波分波器1)で反射された当該高周波はトランジスタ60のドレイン・ソース間を介して帰還回路61に入力されて反射する。さらにトランジスタ60のゲート・ソース間を介して帰還回路62に入力されて反射して、トランジスタ60のゲート端子に同相となるように帰還する。この高周波が発振周波数となる。
Next, the operation of the third embodiment will be described.
The operation of the
発振器が発振動作を行うには、トランジスタとそのトランジスタの各端子に接続された帰還回路とを一巡して得られる利得が正である必要があり、大きい方が発振動作をしやすい。図7に示す高周波発振器は、発振動作を行う基本波を外部の負荷に出力せずにトランジスタ60に帰還しているため、発振器のループ利得が向上し、発振器が発振動作をしやすくなる。さらに、90°ハイブリッド回路2の第3の端子23から発振動作で得られる3倍波が出力される。
なお、ここでは高周波分波器を帰還回路の一つとしてドレイン端子に接続した例を示したが、ゲート端子またはソース端子に当該高周波分波器を備えた場合でも良い。
In order for the oscillator to oscillate, it is necessary that the gain obtained by making a circuit of the transistor and the feedback circuit connected to each terminal of the transistor is positive, and the larger one is easier to oscillate. The high-frequency oscillator shown in FIG. 7 feeds back the fundamental wave for performing the oscillation operation to the
Here, an example is shown in which the high frequency demultiplexer is connected to the drain terminal as one of the feedback circuits, but the high frequency demultiplexer may be provided at the gate terminal or the source terminal.
以上説明したように、実施の形態3の高周波回路によれば、トランジスタの端子のうち少なくとも一つに、帰還回路として構成される実施の形態1の高周波分波器の入力端子が接続され、発振動作を行うようにしたので、高周波分波器で発振動作を行う基本波を帰還させ、その高調波である3倍波を出力することができるため、発振動作を容易に実現することができる。また、直接3倍波に相当する周波数で発振器を構成するよりも、性能の良いトランジスタや共振器を使用できることから、位相雑音を改善することができる。これは、低い周波数を扱う方が損失が低く、寄生成分が小さいためである。 As described above, according to the high frequency circuit of the third embodiment, the input terminal of the high frequency duplexer of the first embodiment configured as a feedback circuit is connected to at least one of the transistor terminals, and the oscillation Since the operation is performed, the fundamental wave that performs the oscillating operation by the high frequency demultiplexer can be fed back and the third harmonic wave that is the harmonic thereof can be output, so that the oscillating operation can be easily realized. In addition, phase noise can be improved because transistors and resonators having better performance can be used than when the oscillator is configured with a frequency corresponding to the third harmonic directly. This is because the loss is lower and the parasitic component is smaller when the low frequency is handled.
また、実施の形態3の高周波回路によれば、第4の端子を開放としたので、分波された3倍波には影響を与えずに、基本波を当該高周波分波器の入力端子に反射して戻すことができる。 Further, according to the high frequency circuit of the third embodiment, since the fourth terminal is opened, the fundamental wave is applied to the input terminal of the high frequency demultiplexer without affecting the demultiplexed third harmonic. It can be reflected back.
実施の形態4.
図8は、実施の形態4の高周波回路として、実施の形態1の高周波分波器を用いたPLLシンセサイザを示す構成図である。
図8において、高周波分波器1は図1に示す高周波分波器であり、対応する部分に同一符号を付してその説明を省略する。高周波分波器1における入力端子100には位相同期回路(PLL)の電圧制御発振器(VCO)70を接続し、90°ハイブリッド回路2の第4の端子24から出力される基本波をPLL回路部71に入力して、PLL回路部71の出力を電圧制御発振器70に与えて負帰還制御を行う構成である。ここで、PLL回路部71は、位相比較器、基準発振器、ループフィルタ及びプリスケーラ等で構成される回路であり、電圧制御発振器70とPLL回路部71で、公知の位相同期回路を構成している。
FIG. 8 is a configuration diagram showing a PLL synthesizer using the high frequency demultiplexer of the first embodiment as the high frequency circuit of the fourth embodiment.
In FIG. 8, the high-
次に、実施の形態4の動作について説明する。
高周波分波器1の動作は実施の形態1と同様である。電圧制御発振器70は電圧を制御することで発振周波数が変化する回路であり、基本波で発振動作を行っている。電圧制御発振器70から出力された基本波は高周波分波器1を介して90°ハイブリッド回路2の第4の端子24から出力される。第4の端子24から出力された基本波はPLL回路部71において基準発振器から出力される基準周波数と位相比較され、PLL回路部71はその位相誤差に応じた電圧を電圧制御発振器70に与える。電圧制御発振器70では与えられた電圧に応じて発振周波数を補正する。この発振動作で生じる3倍波は、90°ハイブリッド回路2の第4の端子24からは出力されず、第3の端子23から出力される。
Next, the operation of the fourth embodiment will be described.
The operation of the
以上説明したように、実施の形態4の高周波回路によれば、実施の形態1の高周波分波器の第4の端子の出力を基準周波数と位相比較する電波として入力する位相同期回路を備え、位相同期回路の電圧制御発振器の出力を当該高周波分波器の入力端子に接続したので、次のような効果がある。すなわち、発振器の出力に接続した高周波分波器で発振動作を行う基本波とその3倍波を分波し、基本波を位相同期回路への入力波、3倍波を外部への出力波とすることで、位相同期回路に用いられるプリスケーラの削減または分周数を小さくでき、PLLシンセサイザの小型化や位相雑音の改善効果を奏する。また、実施の形態3と同様に、直接3倍波に相当する周波数で発振器を構成するよりも、性能の良いトランジスタや共振器を使用できるため、発振器の位相雑音の改善効果を奏する。 As described above, according to the high frequency circuit of the fourth embodiment, the output of the fourth terminal of the high frequency demultiplexer of the first embodiment includes the phase synchronization circuit that inputs the radio wave for phase comparison with the reference frequency, Since the output of the voltage controlled oscillator of the phase locked loop is connected to the input terminal of the high frequency demultiplexer, the following effects are obtained. That is, a fundamental wave that oscillates with a high frequency demultiplexer connected to the output of the oscillator and its third harmonic are demultiplexed, the fundamental wave is input to the phase locked loop, and the third harmonic is output to the outside By doing so, the prescaler used in the phase synchronization circuit can be reduced or the frequency dividing number can be reduced, and the PLL synthesizer can be downsized and the phase noise can be improved. Further, as in the third embodiment, since a transistor or a resonator having better performance can be used than when the oscillator is configured directly at a frequency corresponding to the third harmonic, the effect of improving the phase noise of the oscillator is achieved.
なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
以上のように、この発明に係る高周波分波器及び高周波回路は、複数の入力周波数の電波を分波する高周波分波器と、この高周波分波器を用いた高周波回路の構成に関するものであり、高周波増幅器、高周波発振器及びPLLシンセサイザ等に用いるのに適している。 As described above, the high frequency demultiplexer and the high frequency circuit according to the present invention relate to a configuration of a high frequency demultiplexer that demultiplexes radio waves having a plurality of input frequencies and a high frequency circuit using the high frequency demultiplexer. It is suitable for use in high frequency amplifiers, high frequency oscillators, PLL synthesizers and the like.
1,1a 高周波分波器、2 90°ハイブリッド回路、3 移相回路、5 増幅器、21 第1の端子、22 第2の端子、23 第3の端子、24 第4の端子、31 同相分配器、32 伝送線路、40,43 オープンスタブ、41 ショートスタブ、42 抵抗、60 トランジスタ、61,62 帰還回路、70 電圧制御発振器、71 PLL回路部、100 入力端子。 1, 1a High frequency demultiplexer, 2 90 ° hybrid circuit, 3 phase shift circuit, 5 amplifier, 21 1st terminal, 22 2nd terminal, 23 3rd terminal, 24 4th terminal, 31 in-phase distributor , 32 transmission lines, 40, 43 open stubs, 41 short stubs, 42 resistors, 60 transistors, 61, 62 feedback circuits, 70 voltage controlled oscillators, 71 PLL circuit units, 100 input terminals.
Claims (9)
入力される電波のうち、第1の周波数に関して、前記第1の端子に与える電波よりも90°位相を遅らせた電波を前記第2の端子に与え、前記第2の周波数に関して、前記第1の端子に与える電波よりも90°位相を進めた電波を前記第2の端子に与える移相回路とを備えたことを特徴とする高周波分波器。 When the first terminal is an input terminal, the second terminal is an isolation terminal, the third terminal is a 0 ° output terminal, and the fourth terminal is − A 90 ° hybrid circuit in a relationship to become a 90 ° output terminal;
Of the input radio waves, with respect to the first frequency, a radio wave having a phase delayed by 90 ° with respect to the radio wave applied to the first terminal is applied to the second terminal, and the first frequency is related to the first frequency. A high-frequency branching filter comprising: a phase shift circuit that applies, to the second terminal, a radio wave having a phase advanced by 90 ° with respect to the radio wave applied to the terminal.
前記移相回路は、前記基本波及び前記3倍波を、前記第1の端子と前記第2の端子とに同相かつ等振幅で分配する同相分配器と、
前記同相分配器と前記第2の端子との間に設けられ、前記同相分配器と前記第1の端子との間の電気長よりも前記基本波で1/4波長長い伝送線路とを備えたことを特徴とする請求項1記載の高周波分波器。 The first frequency is a fundamental wave, and the second frequency is a third harmonic,
The phase shift circuit, the in-phase distributor for distributing the fundamental wave and the third harmonic wave to the first terminal and the second terminal with the same phase and equal amplitude;
A transmission line that is provided between the in-phase distributor and the second terminal and that is 1/4 wavelength longer in the fundamental wave than the electrical length between the in-phase distributor and the first terminal; The high frequency demultiplexer according to claim 1, wherein:
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WO2009078095A1 (en) * | 2007-12-18 | 2009-06-25 | Fujitsu Limited | Duplexer, module including the duplexer, and communication apparatus |
US20100295630A1 (en) * | 2009-05-20 | 2010-11-25 | The Regents Of The University Of California | Diplexer synthesis using composite right/left-handed phase-advance/delay lines |
JP2016171554A (en) * | 2014-06-13 | 2016-09-23 | 住友電気工業株式会社 | Electronic equipment |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2024064225A (en) * | 2022-10-27 | 2024-05-14 | 大学共同利用機関法人自然科学研究機構 | Isolator |
JP7694958B2 (en) | 2022-10-27 | 2025-06-18 | 大学共同利用機関法人自然科学研究機構 | Isolator |
Also Published As
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JP6526360B2 (en) | 2019-06-05 |
JPWO2018138829A1 (en) | 2019-06-27 |
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