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US6979865B2 - Cellular mosfet devices and their manufacture - Google Patents

Cellular mosfet devices and their manufacture Download PDF

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US6979865B2
US6979865B2 US10/503,171 US50317104A US6979865B2 US 6979865 B2 US6979865 B2 US 6979865B2 US 50317104 A US50317104 A US 50317104A US 6979865 B2 US6979865 B2 US 6979865B2
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region
diode
area
end region
channel
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US20050082611A1 (en
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Steven Thomas Peake
Christopher Martin Rogers
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NXP BV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths

Definitions

  • This invention relates to cellular MOSFET devices (i.e. cellular insulated-gate field-effect transistor devices), and to their manufacture.
  • the invention relates particularly to the integration of a Schottky diode at a diode area of the body, in parallel with a conduction channel of the MOSFET.
  • Cellular insulated-gate field-effect transistor devices are well known as power switches in a variety of applications.
  • the devices comprise active device cells in a cellular area of a semiconductor body.
  • Each active device cell has a channel-accommodating region of a second conductivity type between a surface-adjacent source region and an underlying drain region that are of a first conductivity type.
  • a gate electrode is dielectrically coupled to the channel-accommodating region for controlling a conduction channel between the source and drain regions in operation of the device.
  • MOSFET metal
  • the gate dielectric need not be oxide.
  • the MOSFET cells may be of DMOS type (having a planar gate at the body surface) or of trench-gate type (having the gate in a trench extending through the channel-accommodating region).
  • the cellular area is laterally bounded by an end structure including a deep end region of the second conductivity type that adjoins the channel-accommodating region. This end region has a greater depth and a higher doping concentration than the channel-accommodating region.
  • the Schottky diode comprises a Schottky barrier integrated between the source electrode (connected to the source region and channel-accommodating region) and a diode portion of the drain region that is of the first conductivity type.
  • Schottky diode areas are incorporated in the MOSFET cells, with the Schottky barriers preferably terminating laterally in an edge of the channel-accommodating region that serves as a guard ring for the Schottky diode.
  • U.S. Pat. No. 4,521,795 discloses Schottky diode integration with both DMOS-type cells and trench-gate cells.
  • United States patent U.S. Pat. No. 6,049,108 and published PCT international patent application WO-00/51167 disclose various specific layout geometries for integrating Schottky diodes in trench-gate MOSFET designs.
  • U.S. Pat. No. 6,049,108 teaches dedicating a selected number of the cells to such diodes at predetermined locations in the cellular area
  • WO-00/51167 discloses integrating the diodes between neighbouring trench-gates in, for example, an elongate stripe cell geometry.
  • the whole contents of U.S. Pat. No. 4,521,795, U.S. Pat. No. 6,049,108 and WO-00/51167 are hereby incorporated herein as reference material.
  • the Schottky diode area is accommodated within the deep end region at a lateral boundary of this cellular area.
  • This deep end region is laterally divided so as to accommodate the diode area therein.
  • a diode portion of the first conductivity type of the drain region extends upwardly through the laterally-divided deep end region that is of the second conductivity type.
  • the Schottky barrier formed with this diode portion terminates laterally in the laterally-divided portions of the deep end region which serve as a field-relief region for the Schottky diode.
  • the overall size and pitch of the active device cells is not affected by this Schottky diode integration, and so the active device cells can be compact. As such, a compact cellular layout with high current capability and low on-resistance can be maintained for the MOSFET.
  • the Schottky diode areas may be accommodated in one or more stripes that extend between cellular areas of the device and/or that extend around a perimeter of the whole cellular area of the device.
  • the deep end regions can be distributed around and throughout the whole active area of the MOSFET, so suppressing parasitic bipolar transistor effects between the source and drain regions and improving the MOSFET ruggedness. These deep end regions are particularly beneficial for incorporation at the boundary of cellular areas that comprise trench-gate cells, when the deep end regions are deeper than the gate trenches.
  • the laterally-divided end-region portions provide good relief of the electric field in the diode portion of the drain region that they laterally bound.
  • the Schottky diode can therefore have good blocking characteristics. Indeed, the laterally divided portions of the deep end region may even have a sufficiently close spacing as to permit depletion of the diode portion of the drain region (across this close spacing) in a blocking state of the device. This is advantageous for the field-relief and for achieving a compact structure.
  • Field trenches containing insulating material may be included in the field-relief region of the diode in order to reduce field spreading beneath the deep end region at the lateral boundary of the diode portion of the drain region.
  • the device may comprise one or more such field trenches which extend to a greater depth in the body than the deep end region and which laterally bound the portions of the deep end region that provide the guard region and field-relief region.
  • the laterally-divided deep end region may provide a simple field-region structure for the diode without any field insulator in this area.
  • a method of manufacturing such cellular MOSFET devices with integrated Schottky diodes comprising the steps of:
  • step (c) forming the active device cells in the cellular area, wherein the cells have a channel-accommodating region of a second conductivity type that adjoins the end region at a boundary of the cellular area, and wherein the end region resulting from the local doping of step (b) has a greater depth and a higher doping concentration than the channel-accommodating region, and
  • This aspect of the invention permits integration of the Schottky diode in the MOSFET device by means of a simple, reliable and low-cost manufacturing process and with good Schottky characteristics.
  • Various masking material layers may be provided over the diode area to mask the diode area during the formation of the active device cells in step (c).
  • the device termination structure may comprise a field insulator.
  • an extra area of the field insulator may be provided also over the diode area before step (c) and serve to mask the diode area during the formation of the active device cells. This extra field-insulator area can then be removed from the diode area before forming the Schottky barrier in step (d).
  • the gate trench is etched into the body in step (c) at windows in an etch-mask layer.
  • an area of the etch-mask layer may be provided over the diode area to mask the diode area during the formation of the active device cells in step (c). This area of the etch-mask layer is removed from the diode area before forming the Schottky barrier in step (d).
  • FIG. 1 is a simple plan view of one example of a trench-gate cellular MOSFET device in accordance with the invention, showing both edge-termination and cross-area configurations for deep end regions that laterally bound cellular areas;
  • FIG. 2 is a cross-sectional view of one example of a cross-area deep end region of such a device as FIG. 1 , taken on the line II—II of FIG. 1 , i.e. between two cellular areas;
  • FIG. 3 is a cross-sectional view of one example of an edge-termination deep end region of such a device as FIG. 1 , taken on the line III—III of FIG. 1 ;
  • FIGS. 4 to 6 are cross-sectional views of the device part of FIG. 2 at successive stages in its manufacture by one example of a method in accordance with the present invention
  • FIG. 7 is a cross-sectional view of another example of an edge-termination structure also in accordance with the invention (similar to that of FIG. 3 but including also deep field trenches), on which are superimposed simulation plots of electric field lines and depletion layers in a blocking state of the Schottky diode;
  • FIG. 8 is a simulation plot of leakage current Ir in 10 ⁇ 3 Amps against reverse voltage Vr in volts, for a Schottky diode having a deep end-region and field-trench boundary as in FIG. 7 , as compared with a Schottky diode having a trench-gate boundary;
  • FIG. 9 is a cross-sectional view of the device part of an edge termination structure, similar to that of FIG. 7 , at a stage in its manufacture also in accordance with the present invention
  • FIG. 10 is a cross-sectional view, similar to FIG. 3 , of the device part of an edge termination structure of a modification also in accordance with the invention, having side-by-side Schottky diodes in the end region.
  • FIGS. 7 and 8 Apart from the simulation plots of FIGS. 7 and 8 , all the drawings are diagrammatic, with the relative dimensions and proportions of various parts of their Figures being shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. Thus, for example, the different spacings between the gate trenches in FIGS. 1 and 2 illustrate the degree to which the proportions are exaggerated or reduced in respective drawings, for convenience and clarity.
  • the same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
  • FIGS. 1 to 3 illustrate an exemplary embodiment of a cellular power MOSFET in accordance with the present invention.
  • each transistor cell has a channel-accommodating region 15 of a second conductivity type (p-type in this example) that separates source and drain regions 13 and 14 , respectively, of a first conductivity type (n-type in this example).
  • the drain region 14 is common to all the cells.
  • the device Being a MOSFET of the trench-gate type, the device has its gate electrode 11 in an insulated trench 20 that extends through the regions 13 and 15 into an underlying portion of the drain region 14 .
  • the individual cells (of elongate stripe geometry in FIG. 1 ) are laterally bounded by this trench-gate 11 .
  • the continuous trench-gate 11 is represented by a broken line (for distinction in the drawing from deep end regions that are described below).
  • the gate 11 is capacitively coupled to the region 15 by an intermediate dielectric layer (not shown), i.e. at the insulated walls of the trench 20 .
  • the application of a voltage signal to gate 11 in the on-state of the device serves, in known manner, for inducing a conduction channel in the region 15 and for controlling current flow in this channel between the source and drain regions 13 and 14 .
  • the source region 13 is located adjacent to the top major surface 10 a of the device body 10 , where regions 13 and 15 are contacted by a source electrode 23 .
  • the trench-gate 11 is insulated from the overlying electrode 23 by an intermediate insulating overlayer 18 (sometimes termed “capping” layer 18 ).
  • the region 14 is a drain-drift region, which may be formed by an epitaxial layer of high resistivity on a more highly-doped substrate 14 a of the same conductivity type.
  • the substrate 14 a is contacted at the bottom major surface 10 b of the device body 10 by a drain electrode 24 .
  • the MOSFET of FIGS. 1 to 3 is a vertical power device structure.
  • the specific cellular device shown in FIG. 1 comprises four cellular areas CA, each of which has a respective end structure at its lateral boundary.
  • the end structure is either an annular edge termination ( FIG. 3 ) in the annular peripheral area PA of the device or a cross stripe structure ( FIG. 2 ) that extends between neighbouring cellular areas CA.
  • the end structure includes an end region 150 of the second conductivity type (i.e. p-type in this example) that extends to a greater depth in the body 10 than do the channel-accommodating region 15 and the gate trench 20 .
  • the end region 150 adjoins the channel-accommodating region 15 and has a higher doping concentration P+ than the channel-accommodating region 15 .
  • the lateral perimeters of these end regions 150 are represented by continuous lines.
  • the end regions 150 of both the annular edge termination and the two cross stripes merge together to form a continuous network pattern.
  • the cross stripes 150 c and 150 b may terminate short of the annular termination region 150 e and so form one or more separate islands in the layout pattern of the end region 150 .
  • FIG. 1 shows only four cross stripes 150 c and 150 b , a larger number of cross stripes or islands 150 c and 150 g may be included in the layout pattern of the end region 150 . Indeed, a large distribution of the deep end regions 150 among the cellular areas CA is beneficial in suppressing parasitic bipolar transistor effects between the source and drain regions 13 and 14 and improving the MOSFET ruggedness.
  • one or more of the deep end regions 150 of these respective end structures in the device of FIGS. 1 to 3 are laterally divided to accommodate a Schottky diode area SA within the deep end region 150 .
  • FIG. 1 illustrates the incorporation of four such diode areas SA within the annular termination region 150 e and two such diode areas SA within the cross stripe regions 150 c . For clarity in the drawing, these diode areas SA are hatched in the plan view of FIG. 1 .
  • the MOSFET device comprises a Schottky diode connected in parallel with the conduction channel of the MOSFET.
  • the diode has a Schottky barrier 100 integrated between the source electrode 23 and a diode portion 14 d of the drain region 14 .
  • This diode portion 14 d of the first conductivity type i.e. n-type in this example
  • the Schottky barrier 100 terminates laterally in the laterally divided portions 150 f of the deep end region 150 , which serve as a guard region and field-relief region for the Schottky diode.
  • FIGS. 2 and 3 diagrammatically show quite a large spacing SY for these field-relief portions 150 f .
  • the spacing SY of the portions 150 f can be quite small, for example sufficiently close as to permit depletion of the diode portion 14 d of the drain region 14 (across this close spacing) in the blocking state. This is advantageous for both increased field-relief and for achieving a compact structure.
  • each of the Schottky diode areas SA is of an elongate stripe geometry. This elongate geometry permits the achievement of both a close spacing SY of the field-relief portions 150 f (i.e. across the stripe) and a large area for the Schottky barrier 100 (i.e. due to the length of the stripe).
  • other layout shapes may be adopted for a Schottky diode area SA, where such would fit within the layout geometry of the deep end region 150 .
  • FIG. 1 shows six separate areas SA in the end-region network 150 e and 150 c . However, these separate areas may merge together into a continuous area SA so as to maximize the area of the Schottky diode. This can save layout area in integrating the Schottky diode, and the spacing SY can be keep small for a given Schottky barrier area and forward voltage of the diode (that is proportional to the Schottky barrier area).
  • FIG. 3 illustrates a Schottky diode area SA in the annular edge termination region 150 e around the annular peripheral area PA of the device.
  • these diode areas SA extend around most of the device perimeter.
  • the device termination structure also includes a field insulator 155 , typically comprising one or more layers of silicon dioxide and/or silicon nitride. This field insulator 155 adjoins the deep end region 150 e where the diode area SA is accommodated but is absent from the drain portion 14 d of the diode.
  • FIG. 1 illustrates a Schottky diode area SA in the annular edge termination region 150 e around the annular peripheral area PA of the device.
  • these diode areas SA extend around most of the device perimeter.
  • the device termination structure also includes a field insulator 155 , typically comprising one or more layers of silicon dioxide and/or silicon nitride. This field insulator 155 adjoins the deep end region 150 e where the diode area SA is accommodated but is
  • FIG. 3 also illustrates inclusion, on the field insulator 155 , of an outwardly-directed field plate 110 g that is connected to the MOSFET gate 11 and an inwardly-directed field plate 110 d that is connected to the MOSFET drain region 14 .
  • the gate connection for field plate 110 g is provided at lateral extensions 11 e and 20 e of the gate 11 and trench 20 in the deep termination region 150 e , as illustrated in FIG. 3 .
  • FIG. 2 illustrates the inclusion of a Schottky diode area SA in a cross stripe region 150 c that extends between two neighbouring cellular areas CA. As shown in FIG. 1 , the active device cells of these two areas CA have their stripe-shaped cell geometry parallel to the region 150 c . In the simple and compact form illustrated in FIG. 2 , there is an absence of the field insulator 155 from the region 150 c.
  • the stripe region 150 b forms part of a gate bus-bar structure that carries a metal gate-connection track (not shown) between neighbouring cellular areas CA.
  • the region 150 b extends to a further part 150 g of the deep end region 150 that is located below the metal gate-terminal bond-pad (also not shown).
  • the metal gate-connection track and the metal gate-terminal bond-pad are connected to lateral extensions 11 b of the trench-gate 11 in the parts 150 b and 150 g of the deep end region 150 .
  • the semiconductor device body 10 is of monocrystalline silicon.
  • the various regions of the device may be as follows.
  • the drain drift region 14 may have a uniform doping n of about 2 ⁇ 10 16 or 3 ⁇ 10 16 phosphorus or arsenic cm ⁇ 3 , or it may have a graded doping from about 1 ⁇ 10 16 cm 3 at the surface 10 a to about 3 ⁇ 10 17 cm ⁇ 3 adjacent to the substrate 14 a .
  • This doping and the thickness of the region 14 depends on the desired voltage blocking capability of the device.
  • the bulk of the source electrode 23 may be of an aluminium-silicon alloy and the layer 23 d may be of, for example, titanium silicide.
  • This silicide layer 23 d forms an ohmic contact to the field-relief portions 150 f in the diode area SA.
  • the silicide layer 23 d may also be included in the active cell areas CA to form good ohmic contacts between the source electrode 23 and the channel region 15 and source region 13 and so reduce source contact resistance.
  • the doping of P+ region 150 may be about 10 18 boron cm ⁇ 3 , whereas that of the channel-accommodating region 15 is typically about 10 17 boron cm ⁇ 3 .
  • the depth (from the surface 10 a ) of P+ region 150 may be about 2.5 ⁇ m (micrometres), for example approaching twice that of the region 15 for a trench-gate depth of about 1.5 ⁇ m or 1.7 ⁇ m.
  • the greater doping and depth of the P+ region 150 pushes the depletion layer (in region 14 ) further towards the substrate 14 a in this boundary area of the cellular areas CA and diode areas SA. This is advantageous in increasing the field-relief for the Schottky diode accommodated in this deep region 150 , as well as in improving the MOSFET ruggedness against breakdown in the active cells of the adjacent areas CA.
  • the gate dielectric layer is typically of thermally grown silicon dioxide or of deposited silicon dioxide, although it may comprise silicon nitride.
  • the trench-gate 11 is of conductively-doped polysilicon, although it may comprise a silicide and/or a refractory metal.
  • the Schottky diode areas SA can be integrated in the device of FIGS. 1 to 3 in a simple, reliable and low-cost manner, using the following process technology that is also in accordance with the present invention.
  • the process includes the steps of:
  • FIG. 4 illustrates stage (b) with a boron ion implantation 50 to provide the P+ region 150 in the epitaxial layer 14 ′.
  • the layout pattern of the P+ region 150 as illustrated in FIG. 1 is defined by an implantation mask 55 , for example of photoresist.
  • a boron dose of about 5 ⁇ 10 13 cm ⁇ 2 ions may be implanted at an energy of about 250 keV. The dose and energy are chosen to make the region 150 more highly doped (P+) than the later-provided channel-accommodating region 15 and deeper in the body 10 than the region 15 and the later-etched trench 20 , 20 e.
  • the field insulator 155 is then provided in the peripheral area PA for the device termination and additionally over the diode areas SA. Thus, additional areas of field insulator 155 are provided over the diode areas SA in the device termination and in the P+ cross regions 150 c.
  • FIG. 5 shows the additional area 155 c of the field insulator layer for a P+ cross region 150 c .
  • the field insulator 155 typically a thick oxide layer, is preferably of deposited material, rather than a thermally grown (LOCOS) oxide. Deposition of the material has less effect on the boron doping concentration of the underlying P+ region 150 .
  • LOC thermally grown
  • the field insulator layer 155 serves to mask the peripheral area PA and diode areas SA of the epitaxial layer 14 ′ during the formation of the active device cells, as illustrated by additional area 155 c in FIG. 6 .
  • the active device cells can be formed in known manner, for example, with (in broad overview) the following stages:
  • the additional areas of the field insulator layer 155 masks the diode areas SA. These additional areas are subsequently removed from the diode areas SA before forming the silicide layer 23 d to provide the Schottky barrier 100 in step (d). Thus, the additional area 155 c is removed, as shown in the corresponding device part of FIG. 2 .
  • the silicide layer 23 d may be deposited on the silicon surface 10 a , and/or the silicide-forming metal (for example, titanium) may be alloyed into the silicon surface 10 a.
  • the silicide-forming metal for example, titanium
  • one or more metal layers are deposited and defined in a photolithographic and etching step into the desired pattern for the source electrode 23 and the metal gate-connection track and the gate bond-pad.
  • metal layers for example, comprising aluminium
  • multiple-levels of metal may be used, particularly if metal parts are desired for field-plates (such as 110 g and 110 d of FIG. 3 ).
  • the back surface 10 b is then metallised to form the drain electrode 34 , after which the wafer body 100 is divided into the individual device bodies 10 .
  • FIG. 7 illustrates one important modification in the field-relief structure for the Schottky diode.
  • the MOSFET termination structure includes a field insulator 155 x accommodated in a field trench 255 that extends to a greater depth in the body than both the deep end region 150 and the gate trenches 20 , 20 e .
  • the field trench 255 x extends close to the interface with the substrate 14 a or even into the substrate 14 a .
  • the spacing SY in the FIG. 7 diode can be larger than that for the diode of FIGS. 2 and 3 .
  • the trenched field insulator 155 x laterally bounds the laterally-divided portions 150 f of the deep end region 150 e that provide the guard region and field-relief region for the Schottky diode.
  • the inclusion of these field trenches 255 serves to reduce field spreading beneath the deep end region 150 e at the lateral boundary of the diode portion 14 d of the drain region 14 , as illustrated by the plots in FIG. 7 .
  • the extent of the depletion layer in the regions 14 and 150 e is represented by the broken line 40
  • the solid lines represent the electric field in these regions 14 and 150 e and in the dielectrics 155 x and 155 .
  • the potential lines in the drain portion 14 d of the diode are well spread (with no field peak concentrations), and are well balanced between the P+ field-relief portions 150 f at opposite sides of the spacing SY.
  • the potential contours are relatively flat as they cross the Schottky spacing SY. This is due to the effect of the dielectric 155 x in the bounding trenches 255 in spreading the potential contours, thereby raising the reverse breakdown of the Schottky diode.
  • the breakdown of the Schottky diode is considerably higher than the breakdown of the active trench-gate MOSFET area. Breakdown will occur in the MOSFET active area, without the usual high leakage current normally seen with planar Schottky diodes, because the Schottky diode is still far from reaching it reverse breakdown limit.
  • FIG. 8 shows a simulation of the near ideal breakdown characteristic (plot B) that results from adopting a FIG. 7 field-relief structure for the Schottky diode.
  • Plot B is for a Schottky diode having a deep end region and deep field trench configuration as in FIG. 7 .
  • Plot C is for a Schottky diode having an n-type diode portion 14 d of width SY, that is laterally bounded by trench-gates of the MOSFET cells, i.e. similar to the Schottky diode structures disclosed in U.S. Pat. No.
  • the area of the Schottky barrier 100 was 2 mm 2 , with a width SY of 1 ⁇ m.
  • the leakage current from the comparison diode is already almost 1 milliAmp at a reverse voltage of 30V.
  • the diode of FIG. 7 configuration has still a minimum leakage current at 30V, with no significant increase until an abrupt breakdown at 60V.
  • the FIG. 7 diode substantially exhibits a typical MOSFET-like leakage profile, but with an increased reverse breakdown capability.
  • a comparable plot is obtainable for the FIG. 3 diode, i.e. with a minimum leakage current still at 30V, but with a lower increased reverse breakdown capability, for example in the range of 45V to 50V.
  • the spacing SY can be upward from about 1 ⁇ m or less.
  • the spacing SY in the FIG. 3 diode should be kept small in order to achieve a low leakage current with effective field relief from the regions 150 f.
  • FIG. 7 diode structure can be formed readily by etching the field trenches 255 after the P+ doping stage of FIG. 4 and before depositing the field insulator 155 , 155 x .
  • FIG. 9 illustrates a particularly advantageous embodiment of how it may be incorporated into the device termination.
  • the diode area SA is masked with a trench-gate etch-mask layer 65 during the formation of the active device cells in step (c).
  • the MOSFET device is of the trench-gate type, having its gate electrode 11 accommodated in a trench 20 .
  • the trench 20 is etched into the body in step (c)(i), at windows in an etch-mask layer 65 that is shown in FIG. 9 .
  • This etch-mask layer 65 may be of, for example, silicon nitride on a thin oxide layer on the body surface 10 a.
  • an additional part 65 x of the etch-mask layer 65 is provided over the diode area SA to mask the diode area SA during the cell formation in steps (c)(i) to (c)(v).
  • FIG. 9 illustrates the situation during the etching of the gate trenches 20 in step (c)(i).
  • the part of the layer 65 on the cellular areas CA in FIG. 9 is the first to be removed as appropriate for carrying out the steps (c)(ii) to (c)(v). Only thereafter, the part 65 x is removed from the diode area SA for the formation of the Schottky barrier 100 in step (d).
  • Part of the etch-mask layer 65 may be retained in the device termination as a part of the field insulator.
  • FIGS. 1 to 7 show only one diode area SA in each laterally-divided deep end region 150 .
  • a plurality of such diode areas SA may be provided in one laterally-divided deep end region 150 .
  • FIG. 10 illustrates one such modification of the FIG. 3 diode, having two side-by-side stripe areas each of width SY. More than two such side-by-side areas may be included, for example to reduce the individual widths SY or to increase the total area of the Schottky barrier 100 .
  • the laterally divided end regions 150 , 150 f may be implanted with such a doping concentration and profile that charge balance is achieved between the p-type depleted portions 150 f and the n-type depleted portion 14 d .
  • Such charge balance is a modified application of the teaching of U.S. Pat. No. 4,754,310 (Philips ref: PHB32740), the whole contents of which are hereby incorporated herein as reference material.
  • the breakdown capability of the integrated Schottky diodes of FIGS. 2 , & 10 can be much improved and the leakage current can be reduced. This would permit the spacing SY to be increased.
  • the higher doped region 14 a of some discrete devices may be formed by dopant diffusion into the back surface 10 b of a high-resistivity substrate that provides the drift region 14 .
  • the region 14 a may be a doped buried layer between a device substrate and the epitaxial low-doped drain region 14 .
  • This buried layer region 14 a may be contacted by an electrode 24 at the front major surface 10 a , via a doped contact region which extends from the surface 10 a to the depth of the buried layer.
  • regions 13 and 14 are of n-type conductivity
  • regions 15 , 150 and 35 are p-type
  • an electron inversion channel is induced in region 15 by the gate 11 .
  • a p-channel device can be manufactured by a method in accordance with the invention.
  • the regions 13 and 14 are of p-type conductivity
  • the regions 15 , 150 and 35 are n-type
  • a hole inversion channel is induced in the region 15 by the gate 11 .
  • the present invention may also be used to integrate Schottky diode areas SA into laterally-divided deep end regions 150 of MOSFETs of the DMOS type.
  • Semiconductor materials other than silicon may be used for devices in accordance with the invention, for example silicon carbide.
  • FIGS. 7 and 9 keeps the P+ field portions 150 f of the end region 150 in the diode area SA.
  • an integrated Schottky diode structure could be formed having its n-type drain diode portion 14 d laterally bounded (throughout its depth from the surface 10 a ) by the insulator-filled field trenches 255 , 155 x , i.e. without the field portions 150 f .
  • the lateral spacing SY that divides the end region 150 (in a modification of FIG.

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US11069772B2 (en) 2018-12-14 2021-07-20 General Electric Company Techniques for fabricating planar charge balanced (CB) metal-oxide-semiconductor field-effect transistor (MOSFET) devices

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AU2003244417A1 (en) 2003-09-02
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