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WO1998039709A1 - Dispositif memoire avec circuit redondant - Google Patents

Dispositif memoire avec circuit redondant Download PDF

Info

Publication number
WO1998039709A1
WO1998039709A1 PCT/DE1998/000643 DE9800643W WO9839709A1 WO 1998039709 A1 WO1998039709 A1 WO 1998039709A1 DE 9800643 W DE9800643 W DE 9800643W WO 9839709 A1 WO9839709 A1 WO 9839709A1
Authority
WO
WIPO (PCT)
Prior art keywords
redundancy
memory
ferroelectric
allocation
lines
Prior art date
Application number
PCT/DE1998/000643
Other languages
German (de)
English (en)
Inventor
Thomas Zettler
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1998039709A1 publication Critical patent/WO1998039709A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/802—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals

Definitions

  • a validation memory cell 21 is provided in the allocation memory 10, which is connected on the input side (DATA connection) to the programming line ENA already mentioned in FIG.
  • the two outputs Dout of the allocation memory cell 19 and the allocation memory cell 20 are each fed to an XNOR gate with two inputs, the other input of the XNOR gate being connected to the respective input terminal DATA of the allocation memory cell.
  • the outputs of the two XNOR gates and the output Dout of the validation memory cell 21 are fed to an AND gate with three inputs.
  • the output AI of the AND gate leads to the redundancy word line RXSEL1, as can best be seen in FIG.
  • the allocation memory cells 19 and 20 and the validation memory cell 21 are each identical built up.
  • the word line RXSEL1 belonging to the redundancy memory cell RS1 is selected when the address pointing to the memory cell S1 is present on the address bus 5. Since the outputs A2, A3 and A4 of the allocation memories 11, 12 and 13 (cf. FIG. 2) are in the state 0, while the output AI of the allocation memory 10 has the value logic "1", the output DIS of the deactivation switch 14 takes on in Figure 2 the value logically "1". This deactivates the address decoder 4 (see FIG. 1), so that interactions between the output of the memory cell S1 and the output of the redundancy memory cell RS1 are prevented.

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif mémoire, notamment un dispositif mémoire à semi-conducteur (1), qui présente les caractéristiques suivantes: au moins une zone (2) de cellules mémoires est constituée de cellules mémoires (S1) qui peuvent être sélectionnées par application d'au moins un signal de sélection dans une zone des lignes de sélection (XSEL 1,...XSEL n) prédéterminés des cellules (S1), lesdites lignes de sélection pouvant être des lignes de mots et/ou des lignes de bits; un circuit redondant (3, 7) est constitué d'au moins une cellule mémoire redondante (RS1), qui peuvent être sélectionnées par application d'un moins un signal de sélection de redondance dans des lignes de sélection de redondance (RXSEL1,... RXSEL4) situées dans une zone de cellules mémoires redondantes (RS1), les lignes de sélection de redondance (RXSEL1,... RXSEL4) pouvant être des lignes de mots redondantes et/ou des lignes de bits redondantes; un circuit sélecteur de lignes de sélection de redondance, dans lequel au moins une information d'attribution peut être mise en mémoire, est conçu de façon que, sur la base de l'information d'attribution, au moins une ligne de sélection de redondance (RXSEL1) puisse être attribuée à au moins une ligne de sélection (XSEL1). Ledit dispositif mémoire nécessite pour la programmation des cellules mémoires redondantes des tensions relativement élevées, de l'ordre de 10 V ou au-dessus, ainsi que des circuits supplémentaires. Selon l'invention, le circuit sélecteur de lignes de sélection comporte, pour la réception des informations d'attribution, au moins une mémoire d'attribution (10, 11, 12, 13) ferroélectrique, notamment une mémoire d'attribution ferroélectrique statique, qui permet d'attribuer d'une manière simple et rapide les cellules mémoires redondantes (RS1) à des cellules mémoires (S1) défectueuses.
PCT/DE1998/000643 1997-03-05 1998-03-04 Dispositif memoire avec circuit redondant WO1998039709A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19708963.1 1997-03-05
DE1997108963 DE19708963C2 (de) 1997-03-05 1997-03-05 Halbleiterdatenspeicher mit einer Redundanzschaltung

Publications (1)

Publication Number Publication Date
WO1998039709A1 true WO1998039709A1 (fr) 1998-09-11

Family

ID=7822312

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/000643 WO1998039709A1 (fr) 1997-03-05 1998-03-04 Dispositif memoire avec circuit redondant

Country Status (2)

Country Link
DE (1) DE19708963C2 (fr)
WO (1) WO1998039709A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7401154B2 (en) 1997-10-30 2008-07-15 Commvault Systems, Inc. Pipelined high speed data transfer mechanism
US9122600B2 (en) 2006-12-22 2015-09-01 Commvault Systems, Inc. Systems and methods for remote monitoring in a computer network
US9170890B2 (en) 2002-09-16 2015-10-27 Commvault Systems, Inc. Combined stream auxiliary copy system and method
US9898213B2 (en) 2015-01-23 2018-02-20 Commvault Systems, Inc. Scalable auxiliary copy processing using media agent resources
US9904481B2 (en) 2015-01-23 2018-02-27 Commvault Systems, Inc. Scalable auxiliary copy processing in a storage management system using media agent resources
US11010261B2 (en) 2017-03-31 2021-05-18 Commvault Systems, Inc. Dynamically allocating streams during restoration of data

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650158B2 (en) 2001-02-21 2003-11-18 Ramtron International Corporation Ferroelectric non-volatile logic elements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0086905A1 (fr) * 1982-02-18 1983-08-31 Deutsche ITT Industries GmbH Système de mémoire avec une matrice intégrée de cellules de mémoire non-volatiles reprogrammables
WO1991014227A1 (fr) * 1990-03-12 1991-09-19 Xicor, Inc. Appareil a redondance programmable par l'utilisateur pour reseaux de memoire
EP0679996A2 (fr) * 1994-04-25 1995-11-02 Matsushita Electric Industrial Co., Ltd. Dispositif de mémoire semi-conducteur et méthode de commande

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200922A (en) * 1990-10-24 1993-04-06 Rao Kameswara K Redundancy circuit for high speed EPROM and flash memory devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0086905A1 (fr) * 1982-02-18 1983-08-31 Deutsche ITT Industries GmbH Système de mémoire avec une matrice intégrée de cellules de mémoire non-volatiles reprogrammables
WO1991014227A1 (fr) * 1990-03-12 1991-09-19 Xicor, Inc. Appareil a redondance programmable par l'utilisateur pour reseaux de memoire
EP0679996A2 (fr) * 1994-04-25 1995-11-02 Matsushita Electric Industrial Co., Ltd. Dispositif de mémoire semi-conducteur et méthode de commande

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"FUSELESS NON-VOLATILE FERROELECTRIC REDUNDANT WORD AND BIT DECODER", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 34, no. 7B, 1 December 1991 (1991-12-01), pages 138 - 140, XP000282528 *
S. WEBER: "FERROELECTRIC CAPACITORS ARE RAMTRON'S BIG IDEA", ELECTRONICS, 18 February 1988 (1988-02-18), pages 91 - 95, XP002073208 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7401154B2 (en) 1997-10-30 2008-07-15 Commvault Systems, Inc. Pipelined high speed data transfer mechanism
US9170890B2 (en) 2002-09-16 2015-10-27 Commvault Systems, Inc. Combined stream auxiliary copy system and method
US9122600B2 (en) 2006-12-22 2015-09-01 Commvault Systems, Inc. Systems and methods for remote monitoring in a computer network
US11416328B2 (en) 2006-12-22 2022-08-16 Commvault Systems, Inc. Remote monitoring and error correcting within a data storage system
US11175982B2 (en) 2006-12-22 2021-11-16 Commvault Systems, Inc. Remote monitoring and error correcting within a data storage system
US10671472B2 (en) 2006-12-22 2020-06-02 Commvault Systems, Inc. Systems and methods for remote monitoring in a computer network
US10346069B2 (en) 2015-01-23 2019-07-09 Commvault Systems, Inc. Scalable auxiliary copy processing in a data storage management system using media agent resources
US10168931B2 (en) 2015-01-23 2019-01-01 Commvault Systems, Inc. Scalable auxiliary copy processing in a data storage management system using media agent resources
US10996866B2 (en) 2015-01-23 2021-05-04 Commvault Systems, Inc. Scalable auxiliary copy processing in a data storage management system using media agent resources
US9904481B2 (en) 2015-01-23 2018-02-27 Commvault Systems, Inc. Scalable auxiliary copy processing in a storage management system using media agent resources
US9898213B2 (en) 2015-01-23 2018-02-20 Commvault Systems, Inc. Scalable auxiliary copy processing using media agent resources
US11513696B2 (en) 2015-01-23 2022-11-29 Commvault Systems, Inc. Scalable auxiliary copy processing in a data storage management system using media agent resources
US11010261B2 (en) 2017-03-31 2021-05-18 Commvault Systems, Inc. Dynamically allocating streams during restoration of data
US11615002B2 (en) 2017-03-31 2023-03-28 Commvault Systems, Inc. Dynamically allocating streams during restoration of data

Also Published As

Publication number Publication date
DE19708963A1 (de) 1998-09-24
DE19708963C2 (de) 1999-06-02

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