[go: up one dir, main page]

WO2007036034A1 - Procede de preparation d'un de de circuit integre a l'imagerie - Google Patents

Procede de preparation d'un de de circuit integre a l'imagerie Download PDF

Info

Publication number
WO2007036034A1
WO2007036034A1 PCT/CA2006/001590 CA2006001590W WO2007036034A1 WO 2007036034 A1 WO2007036034 A1 WO 2007036034A1 CA 2006001590 W CA2006001590 W CA 2006001590W WO 2007036034 A1 WO2007036034 A1 WO 2007036034A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
integrated circuit
vias
layer
circuit die
Prior art date
Application number
PCT/CA2006/001590
Other languages
English (en)
Inventor
Lev Klibanov
Sherri Lynn Griffin
Original Assignee
Chipworks Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipworks Inc. filed Critical Chipworks Inc.
Priority to CN2006800360250A priority Critical patent/CN101287994B/zh
Publication of WO2007036034A1 publication Critical patent/WO2007036034A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2898—Sample preparation, e.g. removing encapsulation, etching

Definitions

  • the invention relates in general to examination and analysis of integrated circuits and, in particular, to methods of preparing an integrated circuit die for imaging to permit a structure and layout of the integrated circuit to be extracted.
  • Fig. Ia is a schematic cross sectional diagram of two metal layers of an integrated circuit die generally indicated by the reference 10. As is well known in the art, each metal layer is covered by an interlayer dielectric (ILD) 12 of a suitable material well known in the art.
  • ILD interlayer dielectric
  • a metal layer N+l is separated from the interlayer dielectric 18 on which it is deposited by a barrier layer 16, also composed of a suitable material well known in the art.
  • the barrier layers 16, 22 prevent the deposited metal layers N+l, N from migrating into the interlayer dielectric 18, 24 onto which they are deposited.
  • a metal line 14 of metal layer N+l is connected to a metal line 20 of metal layer N by a via 26, which is also formed in a manner well known in the art.
  • the barrier layer 16 that separates via 26 from metal layer N is conductive and provides an electrical connection between the via 26 and the metal line 20.
  • passivation layer 12, and any optional barrier material (Fig. Ia) is first removed using a wet or dry etching process or a chemical and/or mechanical polishing process to expose metal lines 14 of metal layer N+l.
  • the integrated circuit die 10 is then placed on a precision stage of the imaging equipment, a scanning electron microscope for example, and tile images are acquired of the area of interest in a manner well known in the art.
  • the metal layer N+l is removed using, for example, a wet or dry etching process or a chemical and/or mechanical polishing process. The process is controlled to remove the metal layer N+l while preserving the integrity of the vias 26, as shown in Fig. Ic.
  • etching solution is selected that will remove the barrier layer 16 as well as the interlayer dielectric 18 while leaving the via 26 intact.
  • the results of that etching step are shown schematically in Fig. Id. If the etching is carefully controlled, the via 26 remains intact and portions of the barrier layer 16r that are shielded by the via 26 and surround the via 26 remain after etching is complete. Thus metal lines 20 of metal layer N and the via 26 are exposed and tile images of the exposed via 26 and metal layer N are acquired in a manner well known in the art.
  • This prior art process can be referred to as a "bottom up” process because the vias are imaged in conjunction with the metal lines to which they are connected at their bottom ends. While this prior art technique works well for integrated circuits constructed using aluminum metal lines and tungsten vias due to the different etching characteristics of the two metals, integrated circuits are now being manufactured using copper metal lines and copper vias. This makes the prior art method very difficult to perform and complicates layout extraction, as will be explained below with reference to FIG. 2.
  • FIG. 2 is a reproduction of an image of a copper damascene integrated circuit prepared using the prior art process described above with reference to FIGs la-Id.
  • the image 30 was acquired using a scanning electron microscope.
  • the integrated circuit die was prepared for imaging using a controlled etching process that removed the metal lines of metal layer N+l and the interlayer dielectric 18 while leaving, to an extent possible, the vias 26.
  • the etching process is difficult to control when the vias and the metal lines are made of the same metal. Consequently, some of the vias 26 are eroded and have an oblong shape in the image.
  • the copper lines 32 and the vias 26 are very similar in shade and it is not consistently clear to which metal line 32 a via 26 is connected. Circuit layout information is therefore difficult to extract and prone to errors.
  • a method of preparing an integrated circuit die for imaging comprising: removing interlayer dielectric material from a metal layer of the integrated circuit die to expose the metal layer; and removing all metal from metal lines of the metal layer without removing a barrier layer that underlies each metal line.
  • a method for extracting circuit information from an integrated circuit die comprising: removing all material covering a first metal layer of the integrated circuit die; etching away all metal from the first layer to completely expose a barrier layer underlying each metal line in the first metal layer; placing the integrated circuit die on a precision stage and acquiring tile images of an area of interest of the integrated circuit die; repeating the removing, etching and placing for each other metal layer; and removing an interlayer dielectric material covering a polycrystalline silicon layer of the integrated circuit die, placing the integrated circuit die on the precision stage and acquiring tile images of polycrystalline silicon layer.
  • a method of preparing an integrated circuit for imaging for the purpose of extracting circuit information comprising removing all material including all metal from the metal lines and metal vias of a metal layer of the integrated circuit die, and acquiring tile images of barrier layers exposed after all of the metal has been removed from the metal lines and the metal vias of the metal layer.
  • Figs. la-Id are schematic diagrams illustrating a technique for preparing an integrated circuit die for imaging in accordance with the prior art
  • FIG. 2 is a reproduction of an image of a copper damascene integrated circuit prepared using the method shown in Figs. la-Id;
  • Fig. 3 is a flow chart providing a high level overview of methods for preparing an integrated circuit die for imaging in accordance with the invention;
  • Figs. 4a-4d are schematic diagrams illustrating a process for preparing an integrated circuit die for imaging in accordance with the invention.
  • Fig. 5 is a reproduction of an image of an integrated circuit prepared in accordance with a process illustrated in Figs. 4a-4c;
  • Fig. 6 is a reproduction of an image of an integrated circuit prepared in accordance with a process illustrated in Figs 4a, 4b and 4d.
  • the invention provides methods of preparing an integrated circuit die for imaging that is useful for preparing integrated circuit dies constructed using any process in which both the metal lines and vias of the integrated circuit are made of the same metal.
  • the methods are very useful for integrated circuits made using an all- copper or an all-aluminum process.
  • the process is equally useful for preparing traditional aluminum/tungsten integrated circuits for imaging.
  • a metal layer of an integrated circuit is exposed, all the metal lines in the metal layer are etched away leaving behind barrier layer material. When images are acquired using a scanning electron microscope, the barrier layer material appears as a first color, typically light grey.
  • etching away the metal lines likewise etches away the vias, leaving a barrier layer that surrounds each via.
  • etched away vias appear in a contrasting color, i.e. dark grey or black.
  • the contrasting colors permit feature extraction software and/or an engineer analyst to readily discriminate between the barrier layer material for the metal lines and the barrier material lining cavities previously occupied by the metal vias.
  • Fig. 3 is a flow chart providing a high level overview of the methods in accordance with the invention.
  • a passivation layer 42 covering the first metal layer (metal layer N+l) is removed (step 42), as shown in Fig. 4b.
  • the passivation layer may be removed using an etching process well known in the art.
  • the integrated circuit is then subjected to a wet or dry etching process to etch away metal lines 14 and vias 26 in order to expose an underlying barrier layer 16 (step 44) .
  • the chip is placed on a precision stage (step 46) and tile images (step 48) are acquired of any area of interest. It is then determined (step 50) whether another metal layer of the integrated circuit exits. If so, an interlayer dielectric (ILD) 18 and any barrier material (not shown) that covers the metal lines is also removed.
  • ILD interlayer dielectric
  • barrier material not shown
  • any process used to remove a passivation layer or an ILD will also remove any barrier material covering metal lines, while leaving the metal lines and any barrier material underlying them.
  • the process branches back to step 44.
  • any remaining interlayer dialectic is removed and the die is once again placed on the precision stage and images are acquired of a polycrystalline layer on which circuit components are formed (step 54) .
  • the tile images for each layer are stitched together in a manner well known in the art (step 56) to form image mosaics.
  • the image mosaics are then vertically aligned, typically using via connections between layers to ensure correct inter-mosaic alignment (step 58) .
  • the aligned image mosaics are then passed to a feature extraction algorithm to reconstruct a parametric representation of the circuit die based on the aligned mosaic images (step 60).
  • Circuit information is then extracted from the parametric representation (step 62), and it is determined whether logical errors exist in the circuit information (step 64) . If so, a report with error exceptions is generated. The report including the error exceptions is passed to engineer analysts who must study the image mosaics and correct any missing or incorrect connections based on information retrieved from the mosaic images. If no errors were detected a report without error exceptions is generated
  • step 68 and the process ends.
  • Figs. 4a-4c illustrate the process described above with reference to Fig. 3 for an integrated circuit constructed using a copper damascene process.
  • the integrated circuit 10 shown in Fig. 4a includes an passivation layer 12 that covers metal lines 14 of metal layer N+l.
  • a via 26 interconnects the metal line 14 with the metal line 20 in the metal layer N.
  • a barrier layer 16 segregates the metal line 14 from interlayer dielectric material 18.
  • Barrier layer 16 is conductive and provides a connection between via 26 and metal line 20 of metal layer N.
  • a barrier layer 22 separates metal line 20 from the interlayer dielectric 24 to ensure that no metal migrates into the interlayer dielectric, which would change its properties.
  • a barrier material (not shown) is applied over metal lines in some integrated circuit manufacturing processes.
  • Fig. 4b shows the integrated circuit die 10 after the passivation layer material 12 has been removed from the metal lines 14 of metal layer N+l. A wet or dry etching process is then used to etch away the metal lines 14 and the vias 26 leaving the barrier layer 16 shown in Fig. 4c.
  • Fig. 5 is a reproduction of an image of a copper/copper integrated circuit prepared for imaging using the process shown in Figs. 4a-4c.
  • the image 80 is a scanning electron microscope image of an area of interest of the integrated circuit die.
  • the barrier layers 82 that underlaid metal lines of the integrated circuit are light grey.
  • the barrier layers that underlaid the vias 84 are dark grey or black, and are easily distinguishable from the barrier layers that underlaid the etched-away metal lines.
  • the vias are also well defined and there is no ambiguity about the metal line with which each via is associated. Since the barrier layers that underlaid the vias are easily distinguished from the barrier layers that underlaid the metal lines, automated layout extraction is very efficient and completes with an extremely low error rate.
  • Fig. 4d shows the integrated circuit 10 prepared in accordance with the invention when the integrated circuit is constructed using aluminum lines 14 and tungsten vias 26.
  • the etching processes shown in FIGs. 4a and 4b removes the aluminum lines but leaves the tungsten vias 26, as shown in Fig. 4d.
  • Fig. 6 is a reproduction of an image of an area of interest of an integrated circuit constructed with aluminum lines and tungsten vias prepared for imaging in accordance with the invention.
  • the image 90 was acquired using a scanning electron microscope.
  • the barrier layers 92 appear as light grey lines while the tungsten vias 94 appear as bright white spots.
  • feature extractions software is readily able to distinguish between background, the barrier layers 92 and the vias 94. Feature extractions is therefore facilitated and automated layout extraction errors are significantly reduced.
  • the invention therefore provides a less time consuming, simpler and more efficient method of preparing an integrated circuit die for imaging.
  • the process provides images with better contrast and is particularly well adapted to use with integrated circuits manufactured using a copper damascene process, although it provides excellent results when used with any known integrated circuit construction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Des dés de circuit intégré destiné à l'imagerie sont préparés par gravure complète de tous les tracés métalliques sans éliminer pour autant les couches barrière qui sont situées sous les tracés métalliques. Les vias métalliques peuvent également être éliminés, plus spécifiquement s'ils sont formés du même métal que les tracés métalliques, comme c'est le cas des circuits de type damasquiné en cuivre. Ceci produit des images à fort contraste et permet ainsi à un logiciel d'extraction de plan de câblage de distinguer rapidement les tracés métalliques et les vias métalliques.
PCT/CA2006/001590 2005-09-29 2006-09-27 Procede de preparation d'un de de circuit integre a l'imagerie WO2007036034A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2006800360250A CN101287994B (zh) 2005-09-29 2006-09-27 制备用于成像的集成电路裸片的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA2,521,675 2005-09-29
CA002521675A CA2521675C (fr) 2005-09-29 2005-09-29 Methode de preparation d'un de a circuits integres pour imagerie

Publications (1)

Publication Number Publication Date
WO2007036034A1 true WO2007036034A1 (fr) 2007-04-05

Family

ID=37899318

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2006/001590 WO2007036034A1 (fr) 2005-09-29 2006-09-27 Procede de preparation d'un de de circuit integre a l'imagerie

Country Status (3)

Country Link
CN (1) CN101287994B (fr)
CA (1) CA2521675C (fr)
WO (1) WO2007036034A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7498181B2 (en) * 2005-09-29 2009-03-03 Chipworks Inc. Method of preparing an integrated circuit die for imaging

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8394721B2 (en) * 2011-05-11 2013-03-12 Nanya Technology Corp. Method for obtaining a layout design for an existing integrated circuit
PL2764376T3 (pl) * 2011-09-27 2017-03-31 Chipworks, Incorporated Sposób rozróżniania pomiędzy urządzeniami z kanałem typu P i kanałem typu N oparty na różnym stopniu wytrawienia
CN111430219B (zh) * 2019-06-27 2022-11-25 合肥晶合集成电路股份有限公司 金属线的去层方法以及器件缺陷检测方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191213A (en) * 1990-07-05 1993-03-02 Olivetti Systems & Networks S.R.L. Integrated circuit structure analysis
US5694481A (en) * 1995-04-12 1997-12-02 Semiconductor Insights Inc. Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
US6263098B1 (en) * 1998-09-11 2001-07-17 The United States Of America As Represented By The Secretary Of The Army Determination of functionality for integrated circuit modules
US6288393B1 (en) * 1998-01-28 2001-09-11 Chipworks Automated method of circuit analysis
US6907583B2 (en) * 2001-10-12 2005-06-14 Semiconductor Insights, Inc. Computer aided method of circuit extraction

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1494120A (zh) * 2002-10-28 2004-05-05 华泰电子股份有限公司 集成电路封装基板的金属电镀方法
US6803284B2 (en) * 2003-02-10 2004-10-12 Macronix International Co., Ltd. Method for manufacturing embedded non-volatile memory with two polysilicon layers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191213A (en) * 1990-07-05 1993-03-02 Olivetti Systems & Networks S.R.L. Integrated circuit structure analysis
US5694481A (en) * 1995-04-12 1997-12-02 Semiconductor Insights Inc. Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
US6288393B1 (en) * 1998-01-28 2001-09-11 Chipworks Automated method of circuit analysis
US6453063B1 (en) * 1998-01-28 2002-09-17 Chipworks Automatic focused ion beam imaging system and method
US6263098B1 (en) * 1998-09-11 2001-07-17 The United States Of America As Represented By The Secretary Of The Army Determination of functionality for integrated circuit modules
US6907583B2 (en) * 2001-10-12 2005-06-14 Semiconductor Insights, Inc. Computer aided method of circuit extraction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7498181B2 (en) * 2005-09-29 2009-03-03 Chipworks Inc. Method of preparing an integrated circuit die for imaging

Also Published As

Publication number Publication date
CA2521675A1 (fr) 2007-03-29
CN101287994B (zh) 2011-06-01
CN101287994A (zh) 2008-10-15
CA2521675C (fr) 2009-11-24

Similar Documents

Publication Publication Date Title
DE102009044961B4 (de) Chipintegrierte HF-Abschirmungen mit rückseitigen Umverdrahtungsleitungen
CN104078343B (zh) 一种栅氧化层缺陷原貌的失效分析方法
CA2260436C (fr) Methode automatisee d'analyse de circuits
JPH10326817A (ja) フリップチップｉｃの基板を介しての検査
WO2007036034A1 (fr) Procede de preparation d'un de de circuit integre a l'imagerie
JPH044525B2 (fr)
US6200823B1 (en) Method for isolation of optical defect images
CN106298565A (zh) 半导体测试结构的制备方法以及测试方法
CN110836905A (zh) 自动识别芯片物理缺陷的失效分析方法
US7498181B2 (en) Method of preparing an integrated circuit die for imaging
CN101226930A (zh) 具有层或结构识别标记的半导体结构及其制作方法和应用
Waite et al. Preparation, imaging, and design extraction of the front-end-of-line and middle-of-line in a 14 nm node finfet device
DE102006004428B4 (de) Technik zum zerstörungsfreien Überwachen der Metallablösung in Halbleiterbauelementen
DE102022111777A1 (de) Integrierte Schaltungsstruktur mit fluoreszierendem Material und zugehörige Verfahren
US6442234B1 (en) X-ray inspection of ball contacts and internal vias
US7402914B2 (en) Semiconductor device featuring overlay-mark used in photolithography process
DE102018210539A1 (de) Zwischenverbindungen mit Hybrid-Metallisierung
Daino et al. Line end voids defectivity improvement on 64 pitch Cu wire interconnects of 14 nm technology
CN115319638B (zh) 芯片研磨方向的确定方法、装置、芯片的研磨方法及系统
DE112020001626T5 (de) Bilderfassungsvorrichtung
US6580072B1 (en) Method for performing failure analysis on copper metallization
JP4300795B2 (ja) 半導体装置及びその検査方法
JPH06101498B2 (ja) 半導体装置の故障解析方法
CN109148315B (zh) 一种芯片内两金属层间通孔连接的辨别方法
CN110071052B (zh) 倒装芯片中失效结构的位置标记方法以及分析方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680036025.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06790754

Country of ref document: EP

Kind code of ref document: A1