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WO2013033034A2 - Method for making high-density electrical interconnections using rivet bonds - Google Patents

Method for making high-density electrical interconnections using rivet bonds Download PDF

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Publication number
WO2013033034A2
WO2013033034A2 PCT/US2012/052552 US2012052552W WO2013033034A2 WO 2013033034 A2 WO2013033034 A2 WO 2013033034A2 US 2012052552 W US2012052552 W US 2012052552W WO 2013033034 A2 WO2013033034 A2 WO 2013033034A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
metal
bond pad
chip
bonding
Prior art date
Application number
PCT/US2012/052552
Other languages
French (fr)
Other versions
WO2013033034A3 (en
Inventor
Kedar G. SHAH
Satinderpall S. Pannu
Angela C. Tooker
Original Assignee
Lawrence Livermore National Security, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lawrence Livermore National Security, Llc filed Critical Lawrence Livermore National Security, Llc
Publication of WO2013033034A2 publication Critical patent/WO2013033034A2/en
Publication of WO2013033034A3 publication Critical patent/WO2013033034A3/en

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Definitions

  • microelectronic components and in particular to a method of making high-density electronic interconnections using rivet bonds.
  • FIG. 1 and 2 show a substrate 10 wire-bonded to a chip 11 by multiple wires, e.g. 12, on bond pads, e.g. 13.
  • wire bonding requires a suitably large footprint since chip and substrate are arranged horizontally and wire-bonds are tall.
  • scalability of the interconnect density may be limited due to interfering wires in a small space.
  • FIG. 3 and 4 show a substrate 20 with bumps, e.g. 22, formed on bond pads, e.g. 23, and a chip 21 also having bumps, e.g. 24, formed on bond pads, e.g. 25. Corresponding bumps between the chip and substrate are aligned and joined together (e.g. 26).
  • Three bumping materials for connecting the chip to the substrate may include for example, but is not limited to, solder (using solder reflow bonding), gold (using for example thermo-compression), and conductive epoxy.
  • the bond pads on the chip face down as shown in Figures 3 and 4.
  • the bond pads on the chip and the substrate are aligned and bonded using a combination of pressure, temperature, and/or ultrasonic energy.
  • flip-chip bonding often require both the chip and the substrate to be prepared with bumps before bonding.
  • conductive epoxies in particular have higher resistances that make them less suitable for some applications.
  • Conductive epoxy bumps are typically deposited using stencil printing, a process that is not considered scalable. And thermo-compression bonding of arrays of metal bumps requires very high forces.
  • a method for electrically connecting two substrates comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; and forming a metal bump at a location of the through-hole so that the metal bump bonds to the first metal bond pad and to the second metal bond pad via the through-hole to establish electrical contact between the first and second metal bond pads.
  • a method for electrically connecting three substrates comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; positioning a third substrate having a third metal bond pad adjacent the first and second substrates; and wire bonding a metal wire to the first, second, and third bond pads by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole, and bonding an opposite end of the metal wire to the third metal bond pad, to establish electrical contact between the first, second, and third metal bond pads.
  • Figure 1 is a side view of a chip electrically connected to a substrate using a wire-bonding process known in the art.
  • Figure 2 is a top view of the wire-bonded chip and substrate of Figure 1.
  • Figure 3 is a side view of a chip electrically connected to a substrate using a flip-chip bonding process known in the art.
  • Figure 4 is a top view of the flip-chip bonded chip and substrate of Figure 3.
  • Figure 5 is a cross-sectional view of a chip and substrate used in an exemplary embodiment of the rivet bonding method of the present invention.
  • Figure 6 is a top view of the chip and substrate in Figure 5.
  • Figure 7 is a cross-sectional view of the chip and substrate of Figures 5 and 6 after rivet bonding.
  • Figure 8 is a top view of the rivet-bonded chip and substrate of Figure 7.
  • Figure 9 is a cross-sectional view of the chip and substrate similar to Figure 7, and also including a wire simultenously bonded by the rivet bond, and also showing a passivating coating.
  • the present invention is generally directed to a method of making high density electrical interconnections between microelectronic components using rivet bonds, in particular, electrical interconnects are formed by rivet bonding through a top substrate onto a bottom substrate using wire-bonding or stud-bumping techniques.
  • This method can be effectively used to rapidly create a high-density of interconnects in a variety of industries and applications, such as for example, microelectronic packaging, implantable bio-medical devices, high-density microelectronics, bio-compatible interconnects, corrosion-resistant electronic devices, etc.
  • Figures 5 and 6 show a first substrate 30 (e.g. chip) and a second substrate 33 to be electrically connected according to the rivet-bonding process of the present invention.
  • the chip 30 has a through-hole or throughbore 32 and an electrically conductive bond pad 31 adjacent (e.g. surrounding) the throughbore 32.
  • the throughbore may be characterized as a metalized throughbore associated with a corresponding bond pad.
  • the bond pad 31 is also connected to a metal trace 35.
  • the chip may be fabricated with a plurality of such metalized through-holes/bond pads to match the location of corresponding bond pads on the substrate.
  • the chip may be made of a variety of materials including but not limited to ceramics, metals, semi-conductors, and polymers.
  • the substrate 33 is also shown having an electrically conductive bond pad 34 on its surface. The chip 30 and substrate 33 are positioned so that the bond pad 34 is substantially vertically aligned with the metalized throughbore 32.
  • the chip may be placed on the substrate as shown in Figures 7 and 8, or suspended close to the substrate (not shown). Rivet bonding is then performed by ultrasonically and/or thermo-compressively forming metal bumps, e.g. 36, at a location of the through-bores so that the metal bump simultaneously bonds to the bond pad of the chip and to the bond pad of the substrate via the throughbore 32, thus making an electrical contact between the bond pads.
  • the metal bumps may be a selected from a variety of metals (such as, but not limited to Al, Au, Pt, Ir-Pt, Ir, Pd, Cu, or alloys of these metals).
  • the present invention may achieve increased density of electrical connections from chip to substrate, increased throughput compared with individual bumping and flipchip bonding of a chip to substrate, high strength bond compared with conductive epoxy bonding, and lower resistance compared with conductive epoxies.
  • Figure 9 shows another exemplary embodiment of the present invention where a wire bond can be made instead of the stud bump in Figures 7 and 8, in order to electrically connect a third component (not shown) via metal wire 40 to the chip 30 and substrate 33.
  • Figure 9 shows wire bonding the metal wire 40 to the first and second bond pads 31 and 34 by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole.
  • an opposite end of the metal wire may be bonded to a third metal bond pad (not shown) of a third component substrate, to establish electrical contact between the first, second, and third metal bond pads.
  • FIG 9 also shows an additional step, after rivet bonding, whereby the tops of the rivets 36 may be passivated with a passivating material 41.
  • the rivet bonds may be coated with a non-conductive epoxy, or with an electrical insulator using a variety of microfabrication processes (chemical vapor deposition, atomic layer deposition, sputtering, evaporation, etc).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A method of making high-density electrical interconnects between micro-electronic components using rivet bonds, by positioning a first substrate over a second substrate to align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate, and forming a metal bump through the through-hole so that the metal bump bonds to and electrically connects the first and second metal bond pads via the through-hole.

Description

METHOD FOR MAKING HIGH-DENSITY ELECTRICAL
INTERCONNECTIONS USING RIVET BONDS CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This patent document claims the benefits and priorities of U.S. Provisional Application No. 61/528,096, filed on August 26, 2011 , hereby incorporated by reference. FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] The United States Government has rights in this invention pursuant to Contract No. DE-AC52-07NA27344 between the United States Department of Energy and Lawrence Livermore National Security, LLC for the operation of Lawrence Livermore National Laboratory.
TECHNICAL FIELD
[0003] This patent document relates to methods of electrically connecting
microelectronic components, and in particular to a method of making high-density electronic interconnections using rivet bonds.
BACKGROUND [0004] In many microtechnology applications, it is necessary to form an electrical connection between two electronic components, such as for example the attachment of MEMS (micro-electro-mechanical systems) to IC chips, and the packaging of IC chips into electronic packages. Some commonly used techniques are wire-bonding, flip-chip bonding, soldering, etc. And a growing number of consumer, medical, and industrial microelectronic devices combine flexible polymer substrates with traditional, stiff semi-conductor chips.
[0005] In wire-bonding, the sites of electrical connection (bond pads), are oriented face-up on both the chip and the substrate. A wire-bonder ultrasonically bonds a thin metal wire between the bond pads to create an electrical connection. For example, Figures 1 and 2 show a substrate 10 wire-bonded to a chip 11 by multiple wires, e.g. 12, on bond pads, e.g. 13. However, wire bonding requires a suitably large footprint since chip and substrate are arranged horizontally and wire-bonds are tall. In addition, scalability of the interconnect density may be limited due to interfering wires in a small space.
[0006] In flip-chip bonding, two substrates are aligned and attached vertically with electrical connections (bumps) between them. For example, Figures 3 and 4 show a substrate 20 with bumps, e.g. 22, formed on bond pads, e.g. 23, and a chip 21 also having bumps, e.g. 24, formed on bond pads, e.g. 25. Corresponding bumps between the chip and substrate are aligned and joined together (e.g. 26). Three bumping materials for connecting the chip to the substrate may include for example, but is not limited to, solder (using solder reflow bonding), gold (using for example thermo-compression), and conductive epoxy. In flip-chip bonding, the bond pads on the chip face down as shown in Figures 3 and 4. The bond pads on the chip and the substrate are aligned and bonded using a combination of pressure, temperature, and/or ultrasonic energy. However, flip-chip bonding often require both the chip and the substrate to be prepared with bumps before bonding. And conductive epoxies in particular have higher resistances that make them less suitable for some applications.
Conductive epoxy bumps are typically deposited using stencil printing, a process that is not considered scalable. And thermo-compression bonding of arrays of metal bumps requires very high forces.
[0007] Therefore, due to the limitations of current interconnect technologies related to interconnect density, processing time, and limited choices of substrates, alternate methods of forming electrical connections are needed to reduce process time and increase throughput, increase the density of interconnects to reduce size and cost, reduce the need for multiple process steps to reduce complexity and increase throughput, provide low resistance electrical contacts, and provide high quality reliable contacts.
SUMMARY [0008] The technology described in this patent document includes devices, systems and methods for making high-density electrical interconnects using rivet bonding, and the rivet- bonded electrical interconnects, devices, and systems produced thereby.
[0009] In one example implementation, a method is provided for electrically connecting two substrates, comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; and forming a metal bump at a location of the through-hole so that the metal bump bonds to the first metal bond pad and to the second metal bond pad via the through-hole to establish electrical contact between the first and second metal bond pads.
[0010] In another example implementation, a method is provided for electrically connecting three substrates, comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; positioning a third substrate having a third metal bond pad adjacent the first and second substrates; and wire bonding a metal wire to the first, second, and third bond pads by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole, and bonding an opposite end of the metal wire to the third metal bond pad, to establish electrical contact between the first, second, and third metal bond pads.
[0011] These and other implementations and various features and operations are described in greater detail in the drawings, the description and the claims.
BRIEF DESCRIPTION OF THE DRAWINGS [0012] Figure 1 is a side view of a chip electrically connected to a substrate using a wire-bonding process known in the art.
[0013] Figure 2 is a top view of the wire-bonded chip and substrate of Figure 1.
[0014] Figure 3 is a side view of a chip electrically connected to a substrate using a flip-chip bonding process known in the art.
[0015] Figure 4 is a top view of the flip-chip bonded chip and substrate of Figure 3. [0016] Figure 5 is a cross-sectional view of a chip and substrate used in an exemplary embodiment of the rivet bonding method of the present invention.
[0017] Figure 6 is a top view of the chip and substrate in Figure 5.
[0018] Figure 7 is a cross-sectional view of the chip and substrate of Figures 5 and 6 after rivet bonding.
[0019] Figure 8 is a top view of the rivet-bonded chip and substrate of Figure 7.
[0020] Figure 9 is a cross-sectional view of the chip and substrate similar to Figure 7, and also including a wire simultenously bonded by the rivet bond, and also showing a passivating coating.
DETAILED DESCRIPTION
[0021] The present invention is generally directed to a method of making high density electrical interconnections between microelectronic components using rivet bonds, in particular, electrical interconnects are formed by rivet bonding through a top substrate onto a bottom substrate using wire-bonding or stud-bumping techniques. This method can be effectively used to rapidly create a high-density of interconnects in a variety of industries and applications, such as for example, microelectronic packaging, implantable bio-medical devices, high-density microelectronics, bio-compatible interconnects, corrosion-resistant electronic devices, etc.
[0022] Turning now to the drawings, Figures 5 and 6 show a first substrate 30 (e.g. chip) and a second substrate 33 to be electrically connected according to the rivet-bonding process of the present invention. The chip 30 has a through-hole or throughbore 32 and an electrically conductive bond pad 31 adjacent (e.g. surrounding) the throughbore 32. As such, the throughbore may be characterized as a metalized throughbore associated with a corresponding bond pad. As shown in Figure 6, the bond pad 31 is also connected to a metal trace 35. The chip may be fabricated with a plurality of such metalized through-holes/bond pads to match the location of corresponding bond pads on the substrate. The chip may be made of a variety of materials including but not limited to ceramics, metals, semi-conductors, and polymers. The substrate 33 is also shown having an electrically conductive bond pad 34 on its surface. The chip 30 and substrate 33 are positioned so that the bond pad 34 is substantially vertically aligned with the metalized throughbore 32.
[0023] After alignment, the chip may be placed on the substrate as shown in Figures 7 and 8, or suspended close to the substrate (not shown). Rivet bonding is then performed by ultrasonically and/or thermo-compressively forming metal bumps, e.g. 36, at a location of the through-bores so that the metal bump simultaneously bonds to the bond pad of the chip and to the bond pad of the substrate via the throughbore 32, thus making an electrical contact between the bond pads. The metal bumps may be a selected from a variety of metals (such as, but not limited to Al, Au, Pt, Ir-Pt, Ir, Pd, Cu, or alloys of these metals). And various techniques for forming and applying the metal bumps may be employed, such as for example but not limited to using wire-bonder, stud-bumper, or flip-chip bonder. In this manner, the present invention may achieve increased density of electrical connections from chip to substrate, increased throughput compared with individual bumping and flipchip bonding of a chip to substrate, high strength bond compared with conductive epoxy bonding, and lower resistance compared with conductive epoxies.
100241 Figure 9 shows another exemplary embodiment of the present invention where a wire bond can be made instead of the stud bump in Figures 7 and 8, in order to electrically connect a third component (not shown) via metal wire 40 to the chip 30 and substrate 33. In particular, Figure 9 shows wire bonding the metal wire 40 to the first and second bond pads 31 and 34 by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole. And an opposite end of the metal wire may be bonded to a third metal bond pad (not shown) of a third component substrate, to establish electrical contact between the first, second, and third metal bond pads. In this manner, the rivet bond electrically connects three components- two vertically, and one horizontally. Figure 9 also shows an additional step, after rivet bonding, whereby the tops of the rivets 36 may be passivated with a passivating material 41. In particular, the rivet bonds may be coated with a non-conductive epoxy, or with an electrical insulator using a variety of microfabrication processes (chemical vapor deposition, atomic layer deposition, sputtering, evaporation, etc).
[0025] Although the description above contains many details and specifics, these should not be construed as limiting the scope of the invention or of what may be claimed, but as merely providing illustrations of some of the presently preferred embodiments of this invention. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document. The features of the embodiments described herein may be combined in all possible combinations of methods, apparatus, modules, systems, and computer program products. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments.
[0026] Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more." All structural and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element or component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. 1 12, sixth paragraph, unless the element is expressly recited using the phrase "means for."

Claims

CLAIMS We claim:
1. A method of electrically connecting two substrates, comprising:
positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; and
forming a metal bump at a location of the through-hole so that the metal bump bonds to the first metal bond pad and to the second metal bond pad via the through- hole to establish electrical contact between the first and second metal bond pads.
2. The method of claim 1 ,
further comprising passivating the metal bump with a non-conductive material.
3. A method of electrically connecting three substrates, comprising:
positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate;
positioning a third substrate having a third metal bond pad adjacent the first and second substrates; and
wire bonding a metal wire to the first, second, and third bond pads by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole, and bonding an opposite end of the metal wire to the third metal bond pad, to establish electrical contact between the first, second, and third metal bond pads.
4. The method of claim 3, further comprising passivating the metal wire with a non-conductive material.
PCT/US2012/052552 2011-08-26 2012-08-27 Method for making high-density electrical interconnections using rivet bonds WO2013033034A2 (en)

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Publication number Priority date Publication date Assignee Title
US5048747A (en) * 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
TW536794B (en) * 1999-02-26 2003-06-11 Hitachi Ltd Wiring board and its manufacturing method, semiconductor apparatus and its manufacturing method, and circuit board
US6863209B2 (en) * 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
US6680128B2 (en) * 2001-09-27 2004-01-20 Agilent Technologies, Inc. Method of making lead-free solder and solder paste with improved wetting and shelf life
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US7282433B2 (en) * 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads

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