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WO2013033034A2 - Procédé de formation d'interconnexions électriques haute densité à l'aide de liens de type rivets - Google Patents

Procédé de formation d'interconnexions électriques haute densité à l'aide de liens de type rivets Download PDF

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Publication number
WO2013033034A2
WO2013033034A2 PCT/US2012/052552 US2012052552W WO2013033034A2 WO 2013033034 A2 WO2013033034 A2 WO 2013033034A2 US 2012052552 W US2012052552 W US 2012052552W WO 2013033034 A2 WO2013033034 A2 WO 2013033034A2
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WO
WIPO (PCT)
Prior art keywords
substrate
metal
bond pad
chip
bonding
Prior art date
Application number
PCT/US2012/052552
Other languages
English (en)
Other versions
WO2013033034A3 (fr
Inventor
Kedar G. SHAH
Satinderpall S. Pannu
Angela C. Tooker
Original Assignee
Lawrence Livermore National Security, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lawrence Livermore National Security, Llc filed Critical Lawrence Livermore National Security, Llc
Publication of WO2013033034A2 publication Critical patent/WO2013033034A2/fr
Publication of WO2013033034A3 publication Critical patent/WO2013033034A3/fr

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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Definitions

  • microelectronic components and in particular to a method of making high-density electronic interconnections using rivet bonds.
  • FIG. 1 and 2 show a substrate 10 wire-bonded to a chip 11 by multiple wires, e.g. 12, on bond pads, e.g. 13.
  • wire bonding requires a suitably large footprint since chip and substrate are arranged horizontally and wire-bonds are tall.
  • scalability of the interconnect density may be limited due to interfering wires in a small space.
  • FIG. 3 and 4 show a substrate 20 with bumps, e.g. 22, formed on bond pads, e.g. 23, and a chip 21 also having bumps, e.g. 24, formed on bond pads, e.g. 25. Corresponding bumps between the chip and substrate are aligned and joined together (e.g. 26).
  • Three bumping materials for connecting the chip to the substrate may include for example, but is not limited to, solder (using solder reflow bonding), gold (using for example thermo-compression), and conductive epoxy.
  • the bond pads on the chip face down as shown in Figures 3 and 4.
  • the bond pads on the chip and the substrate are aligned and bonded using a combination of pressure, temperature, and/or ultrasonic energy.
  • flip-chip bonding often require both the chip and the substrate to be prepared with bumps before bonding.
  • conductive epoxies in particular have higher resistances that make them less suitable for some applications.
  • Conductive epoxy bumps are typically deposited using stencil printing, a process that is not considered scalable. And thermo-compression bonding of arrays of metal bumps requires very high forces.
  • a method for electrically connecting two substrates comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; and forming a metal bump at a location of the through-hole so that the metal bump bonds to the first metal bond pad and to the second metal bond pad via the through-hole to establish electrical contact between the first and second metal bond pads.
  • a method for electrically connecting three substrates comprising: positioning a first substrate over a second substrate to substantially align a through-hole and adjacent first metal bond pad of the first substrate with a second metal bond pad of the second substrate; positioning a third substrate having a third metal bond pad adjacent the first and second substrates; and wire bonding a metal wire to the first, second, and third bond pads by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole, and bonding an opposite end of the metal wire to the third metal bond pad, to establish electrical contact between the first, second, and third metal bond pads.
  • Figure 1 is a side view of a chip electrically connected to a substrate using a wire-bonding process known in the art.
  • Figure 2 is a top view of the wire-bonded chip and substrate of Figure 1.
  • Figure 3 is a side view of a chip electrically connected to a substrate using a flip-chip bonding process known in the art.
  • Figure 4 is a top view of the flip-chip bonded chip and substrate of Figure 3.
  • Figure 5 is a cross-sectional view of a chip and substrate used in an exemplary embodiment of the rivet bonding method of the present invention.
  • Figure 6 is a top view of the chip and substrate in Figure 5.
  • Figure 7 is a cross-sectional view of the chip and substrate of Figures 5 and 6 after rivet bonding.
  • Figure 8 is a top view of the rivet-bonded chip and substrate of Figure 7.
  • Figure 9 is a cross-sectional view of the chip and substrate similar to Figure 7, and also including a wire simultenously bonded by the rivet bond, and also showing a passivating coating.
  • the present invention is generally directed to a method of making high density electrical interconnections between microelectronic components using rivet bonds, in particular, electrical interconnects are formed by rivet bonding through a top substrate onto a bottom substrate using wire-bonding or stud-bumping techniques.
  • This method can be effectively used to rapidly create a high-density of interconnects in a variety of industries and applications, such as for example, microelectronic packaging, implantable bio-medical devices, high-density microelectronics, bio-compatible interconnects, corrosion-resistant electronic devices, etc.
  • Figures 5 and 6 show a first substrate 30 (e.g. chip) and a second substrate 33 to be electrically connected according to the rivet-bonding process of the present invention.
  • the chip 30 has a through-hole or throughbore 32 and an electrically conductive bond pad 31 adjacent (e.g. surrounding) the throughbore 32.
  • the throughbore may be characterized as a metalized throughbore associated with a corresponding bond pad.
  • the bond pad 31 is also connected to a metal trace 35.
  • the chip may be fabricated with a plurality of such metalized through-holes/bond pads to match the location of corresponding bond pads on the substrate.
  • the chip may be made of a variety of materials including but not limited to ceramics, metals, semi-conductors, and polymers.
  • the substrate 33 is also shown having an electrically conductive bond pad 34 on its surface. The chip 30 and substrate 33 are positioned so that the bond pad 34 is substantially vertically aligned with the metalized throughbore 32.
  • the chip may be placed on the substrate as shown in Figures 7 and 8, or suspended close to the substrate (not shown). Rivet bonding is then performed by ultrasonically and/or thermo-compressively forming metal bumps, e.g. 36, at a location of the through-bores so that the metal bump simultaneously bonds to the bond pad of the chip and to the bond pad of the substrate via the throughbore 32, thus making an electrical contact between the bond pads.
  • the metal bumps may be a selected from a variety of metals (such as, but not limited to Al, Au, Pt, Ir-Pt, Ir, Pd, Cu, or alloys of these metals).
  • the present invention may achieve increased density of electrical connections from chip to substrate, increased throughput compared with individual bumping and flipchip bonding of a chip to substrate, high strength bond compared with conductive epoxy bonding, and lower resistance compared with conductive epoxies.
  • Figure 9 shows another exemplary embodiment of the present invention where a wire bond can be made instead of the stud bump in Figures 7 and 8, in order to electrically connect a third component (not shown) via metal wire 40 to the chip 30 and substrate 33.
  • Figure 9 shows wire bonding the metal wire 40 to the first and second bond pads 31 and 34 by bonding one end of the metal wire at a location of the through-hole so as to bond to the first metal bond pad and to the second metal bond pad via the through-hole.
  • an opposite end of the metal wire may be bonded to a third metal bond pad (not shown) of a third component substrate, to establish electrical contact between the first, second, and third metal bond pads.
  • FIG 9 also shows an additional step, after rivet bonding, whereby the tops of the rivets 36 may be passivated with a passivating material 41.
  • the rivet bonds may be coated with a non-conductive epoxy, or with an electrical insulator using a variety of microfabrication processes (chemical vapor deposition, atomic layer deposition, sputtering, evaporation, etc).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de formation d'interconnexions électriques haute densité entre des composants microélectroniques à l'aide de liens de type rivets, ceci en positionnant un premier substrat sur un second substrat afin d'aligner un trou traversant et une première plage de contact métallique adjacente du premier substrat avec une seconde plage de contact métallique du second substrat, et en formant une bosse métallique à travers le trou traversant de sorte que la bosse métallique se lie aux première et seconde plages de contact métalliques et les connecte électriquement via le trou traversant.
PCT/US2012/052552 2011-08-26 2012-08-27 Procédé de formation d'interconnexions électriques haute densité à l'aide de liens de type rivets WO2013033034A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161528096P 2011-08-26 2011-08-26
US61/528,096 2011-08-26

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Publication Number Publication Date
WO2013033034A2 true WO2013033034A2 (fr) 2013-03-07
WO2013033034A3 WO2013033034A3 (fr) 2013-04-25

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Application Number Title Priority Date Filing Date
PCT/US2012/052552 WO2013033034A2 (fr) 2011-08-26 2012-08-27 Procédé de formation d'interconnexions électriques haute densité à l'aide de liens de type rivets

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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5048747A (en) * 1989-06-27 1991-09-17 At&T Bell Laboratories Solder assembly of components
TW536794B (en) * 1999-02-26 2003-06-11 Hitachi Ltd Wiring board and its manufacturing method, semiconductor apparatus and its manufacturing method, and circuit board
US6863209B2 (en) * 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
US6680128B2 (en) * 2001-09-27 2004-01-20 Agilent Technologies, Inc. Method of making lead-free solder and solder paste with improved wetting and shelf life
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US7282433B2 (en) * 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads

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