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WO2018167601A1 - Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Download PDF

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WO2018167601A1
WO2018167601A1 PCT/IB2018/051416 IB2018051416W WO2018167601A1 WO 2018167601 A1 WO2018167601 A1 WO 2018167601A1 IB 2018051416 W IB2018051416 W IB 2018051416W WO 2018167601 A1 WO2018167601 A1 WO 2018167601A1
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insulator
oxide
conductor
region
transistor
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PCT/IB2018/051416
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English (en)
Japanese (ja)
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山崎舜平
種村和幸
松林大介
村川努
竹内敏彦
駒形大樹
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株式会社半導体エネルギー研究所
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Priority to JP2019505304A priority Critical patent/JPWO2018167601A1/ja
Publication of WO2018167601A1 publication Critical patent/WO2018167601A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • Non-Patent Document 6 a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and an LSI and a display using the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8). .
  • selective reduction in resistance of the oxide 230 is performed by forming the insulator 274 over the oxide 230 and the conductor 260 over the oxide 230 with the insulator 273 interposed therebetween. Can do. That is, the resistance of the oxide 230 is reduced in a self-aligning manner by using the conductor 260 functioning as a gate electrode as a mask. Therefore, when the plurality of transistors 200 are formed at the same time, variation in electrical characteristics between the transistors can be reduced. Further, the channel length of the transistor 200 is determined by the width of the conductor 260, and the transistor 200 can be miniaturized by setting the width of the conductor 260 to a minimum processing dimension.
  • An insulator such as strontium (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) can be used as a single layer or a stacked layer.
  • strontium (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) can be used as a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220, the insulator 222, and the insulator 224 function as gate insulators.
  • the insulator 222 is so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the physical film thickness can be maintained and the gate potential during transistor operation can be reduced.
  • the oxide 230 preferably has a stacked structure with oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the element M is a metal element.
  • As the oxide 230c a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the region 231 and the region 232 are regions obtained by adding impurities to the metal oxide provided as the oxide 230. Note that the region 231 has higher conductivity than the region 234. Further, the region 232 has lower conductivity than the region 231 and higher conductivity than the region 234.
  • the transistor 200 when the resistance of the region 232 is reduced, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; Mobility can be increased.
  • the region 232 since the region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed.
  • leakage current at the time of non-conduction can be reduced.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a large band gap.
  • the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, or neodymium. It is preferable to use a metal oxide such as one or a plurality selected from hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • the insulator 252 preferably suppresses oxygen diffusion in order to efficiently supply oxygen in the excess oxygen region of the insulator 250 to the oxide 230.
  • oxygen diffusion to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen in the excess oxygen region can be suppressed.
  • the insulator 250 and the insulator 252 may function as part of the gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the insulator 252 is preferably formed using a metal oxide that is a high-k material with a high relative dielectric constant. By setting it as the said laminated structure, it can be set as the laminated structure stable with respect to a heat
  • EOT equivalent oxide thickness
  • the on-state current can be improved without weakening the influence of the electric field from the conductor 260.
  • leakage current can be suppressed by maintaining the distance between the conductor 260 and the oxide 230 depending on the physical thickness of the insulator 250 and the insulator 252.
  • the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily increased. Can be adjusted appropriately.
  • the conductor 260b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductor having high conductivity is preferably used.
  • a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, the top surface and the side surface of the conductor 260, the side surface of the insulator 250, and the side surface of the insulator 252 are formed. Can be covered. Accordingly, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260, the insulator 250, and the insulator 252. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.
  • a transistor when a transistor is miniaturized and a channel length is formed to be about 10 nm to 30 nm, an impurity element contained in a structure provided around the transistor 200 is diffused, so that a region 231a and a region 231b are formed. There is a risk of electrical conduction.
  • the first gate potential is 0 V, the source region and the drain region can be prevented from being electrically connected.
  • the thicknesses of the insulator 273 and the insulator 274 may be adjusted as appropriate depending on the material used.
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.
  • the insulator 274 and the conductor in contact with the insulator 280 have a function of suppressing transmission of impurities such as water or hydrogen, like the conductor 205a.
  • a conductive material For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from the upper layer than the insulator 280 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.
  • a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • a flexible substrate may be used as the substrate.
  • a method for providing a transistor over a flexible substrate there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled off and transferred to a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate may have elasticity.
  • the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • the flexible substrate for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used.
  • the flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used as the flexible substrate.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.
  • Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. There are oxynitrides having silicon and nitrides having silicon and hafnium.
  • silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • the insulator 222 is preferably formed using silicon oxide or silicon oxynitride which is stable against heat.
  • the gate insulator has a heat-stable film and a laminated structure with a high relative dielectric constant, so that the equivalent oxide thickness (EOT) of the gate insulator can be reduced while maintaining the physical film thickness. It becomes.
  • the on-state current can be improved without weakening the influence of the electric field from the gate electrode. Further, leakage current can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed depending on the physical thickness of the gate insulator.
  • the insulator 212, the insulator 216, the insulator 271 and the insulator 280 preferably include an insulator having a low relative dielectric constant.
  • the insulator 212, the insulator 216, and the insulator 280 are doped with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to include silicon oxide, silicon oxide having holes, resin, or the like.
  • the insulator 212, the insulator 216, and the insulator 280 are added with silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon, and nitrogen. It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • the conductor 260, the conductor 203, the conductor 205, and the conductor 240 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium
  • a material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in the distortion.
  • it is difficult to check a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • a metal oxide with low carrier density is preferably used.
  • the impurity concentration in the metal oxide may be lowered and the defect level density may be lowered.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the metal oxide has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
  • the metal oxide used for the semiconductor of the transistor a thin film with high crystallinity is preferably used.
  • the stability or reliability of the transistor can be improved.
  • the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film.
  • a high temperature or laser heating process is required in order to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate. Therefore, the cost of the manufacturing process increases and the throughput also decreases.
  • Non-Patent Document 1 Non-Patent Document 1
  • Non-Patent Document 2 An In—Ga—Zn oxide having a CAAC structure
  • CAAC-IGZO In—Ga—Zn oxide having a CAAC structure
  • nc-IGZO In 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and regularity is not observed in crystal orientation between different regions. Yes.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by irradiation of electron beams with respect to the thin films of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity.
  • a complete amorphous structure could not be confirmed in IGZO.
  • CAAC-IGZO thin film and the nc-IGZO thin film have higher stability against electron beam irradiation than the low crystalline IGZO thin film. Therefore, a CAAC-IGZO thin film or an nc-IGZO thin film is preferably used as a semiconductor of the transistor.
  • a transistor using a metal oxide has extremely small leakage current in a non-conducting state. Specifically, an off-current per 1 ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 ⁇ 24 A / ⁇ m).
  • yA / ⁇ m 10 ⁇ 24 A / ⁇ m.
  • Non-Patent Document 8 an application of a transistor using a metal oxide to a display device using a characteristic that the leakage current of the transistor is low has been reported (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second.
  • the number of switching of images per second is called a refresh rate.
  • the refresh rate may be referred to as a drive frequency.
  • Such high-speed screen switching that is difficult for human eyes to perceive is considered as a cause of eye fatigue.
  • power consumption of the display device can be reduced by driving at a reduced refresh rate.
  • Such a driving method is called idling stop (IDS) driving.
  • IDS idling stop
  • the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level is formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide.
  • the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIGS. 3 to 11 (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed.
  • ALD does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • an aluminum oxide film is formed as the insulator 210 by a sputtering method.
  • the insulator 210 may have a multilayer structure.
  • an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method.
  • an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed on the aluminum oxide by a sputtering method.
  • the insulator 210 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film as an insulating film functioning as an etching stopper film.
  • a conductive film to be the conductor 203a is formed.
  • the conductive film preferably includes a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductor to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 203a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
  • a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out of the conductor 203a even when a metal that easily diffuses such as copper is used in the conductor 203b described later.
  • a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203b.
  • the conductive film to be the conductor 203a and a part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed.
  • the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening.
  • the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 3).
  • part of the insulator 212 may be removed by the CMP treatment.
  • an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216.
  • the opening may be formed by wet etching, but dry etching is preferable for fine processing.
  • the conductive film to be the conductor 205a desirably includes a conductive material having a function of suppressing permeation of oxygen.
  • a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a BLD method, an ALD method, or the like.
  • tantalum nitride is formed by a sputtering method as the conductive film to be the conductor 205a.
  • a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed by a CVD method as the conductive film to be the conductor 205b, and tungsten is formed by a CVD method on the titanium nitride.
  • CMP is performed to remove part of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, so that the insulator 216 is exposed.
  • the conductive films to be the conductors 205a and 205b remain only in the openings. Accordingly, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 3). Note that part of the insulator 212 may be removed by the CMP treatment.
  • the insulator 220 is formed over the insulator 216 and the conductor 205.
  • the insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 212 by a CVD method.
  • the insulator 222 is formed over the insulator 220.
  • an insulator including one or both of aluminum and hafnium may be formed.
  • the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3).
  • silicon oxide is formed as the insulator 224 by a CVD method.
  • treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed.
  • oxygen is added from the insulator 222 to the insulator 224, so that an excess oxygen region can be easily formed in the insulator 224.
  • impurities such as hydrogen and water contained in the insulator 224 can be removed.
  • plasma treatment including oxygen may be performed in a reduced pressure state.
  • an apparatus having a power source that generates high-density plasma using microwaves for example.
  • a power source for applying RF (Radio Frequency) may be provided on the substrate side.
  • High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side.
  • plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.
  • an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 4).
  • the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • the proportion of oxygen contained in the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.
  • the oxide film is formed by a sputtering method
  • the In-M-Zn oxide target can be used.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed.
  • a transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed.
  • the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 5).
  • the insulator 224 may be processed into an island shape.
  • the insulator 222 can be used as an etching stopper film.
  • the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased.
  • the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.
  • a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that end portions of the side surfaces of the oxide 230a and the oxide 230b and an end portion of the upper surface of the oxide 230b are curved.
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
  • the oxide film may be processed by a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • Cleaning is performed in order to remove the impurities and the like.
  • the cleaning method there are wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
  • the wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning using pure water or carbonated water may be performed.
  • ultrasonic cleaning using pure water or carbonated water is performed.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • the oxide film 230C, the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b. Film (see FIG. 6).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
  • oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film 250A is exposed to the oxygen plasma, whereby oxygen is generated into the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
  • the insulating film 252A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 252A is formed by a sputtering method
  • ions and sputtered particles exist between the target and the substrate.
  • the target is connected to a power source and is supplied with the potential E0.
  • the substrate is given a potential E1 such as a ground potential.
  • the substrate may be electrically floating.
  • the magnitude relationship between the potentials is E2> E1> E0.
  • Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles sputtered from the target are ejected.
  • the sputtered particles adhere to and deposit on the film formation surface to form a film.
  • some ions recoil by the target pass through a film formed as recoil ions, and may be taken into the insulating film 250A and the insulator 224 in contact with the deposition surface.
  • ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulating film 250 ⁇ / b> A and the insulator 224.
  • a film is formed in an oxygen gas atmosphere using a sputtering apparatus, so that oxygen is supplied to the insulating film 250A and the insulator 224 while the insulating film 252A is formed. Can be introduced. In particular, when one or both of aluminum and hafnium having a barrier property are used for the insulating film 252A, oxygen introduced into the insulator 250 can be effectively contained.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed.
  • oxygen is added from the insulating film 252A to the insulating film 250A and the insulator 224, so that an excess oxygen region can be easily formed in the insulating film 250A and the insulator 224.
  • the insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxidation of the conductive film 260B can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230a, the oxide 230b, and the oxide film 230C through the conductive film 260A, the conductive film 260B, and the insulating film 250A. In this embodiment, aluminum oxide is formed as the insulating film 270A by an ALD method.
  • the insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.
  • silicon oxide is formed by a CVD method as the insulating film 271A.
  • the insulating film 271A is etched to form the insulator 271.
  • the insulator 271 functions as a hard mask.
  • the side surface of the insulator 250, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.
  • the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, the insulator 270, and the insulator 271 are formed so that at least a part thereof overlaps with the conductor 205, the oxide 230a, and the oxide 230b. To do.
  • the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are preferably in the same plane.
  • the same surface shared by the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 is preferably substantially perpendicular to the substrate. . That is, in the cross-sectional shape, the insulator 250, the insulator 252, the conductor 260 a, the conductor 260 b, and the insulator 270 are preferably as acute and large as possible with respect to the top surface of the oxide 230.
  • a cross-sectional shape of the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, and the side surfaces of the insulator 270 and the top surface of the oxide 230 may be acute.
  • the angle formed by the side surfaces of the insulator 250, the conductor 260a, the conductor 260b, and the insulator 270 and the upper surface of the oxide 230 is preferably as large as possible.
  • the post-process may be performed without removing the hard mask (insulator 271) after the processing.
  • an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the insulator 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 8).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage.
  • the insulating film 272 ⁇ / b> A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the step portion formed by the conductor 260 and the like. be able to.
  • the oxide film 230C is etched at the same time by the above-described etching, so that the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) is formed.
  • the oxide 230 may be formed by an etching step different from the above etching.
  • the oxide film 230C may be processed by a wet etching process. Etching residues during dry etching can be washed with the wet etching solution.
  • the upper part of the region where the oxide 230b does not overlap with the insulator 250 may be etched by the above process.
  • the thickness of the region of the oxide 230b that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
  • the oxide 230 may have a film thickness in a region overlapping with the insulator 250 larger than that in a region overlapping with the insulator 272. is there.
  • the insulator 270 can remain even if the insulating film 272A over the insulator 270 is removed. Further, the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is set higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C, thereby oxidizing the oxide. The insulating film 272A on the side surfaces of the oxide 230a and the oxide 230b through the film 230C can be removed.
  • the insulating film 272 ⁇ / b> A may remain on the side surface of the oxide 230. In that case, the film property of an interlayer film formed in a later process can be improved. In addition, since the insulator remains on the side surface of the oxide 230, impurities such as water or hydrogen mixed in the oxide 230 can be reduced, and oxygen can be prevented from being outwardly diffused from the oxide 230. is there.
  • the structure in which the insulating film 272 ⁇ / b> A remains is formed in contact with the side surface of the oxide 230, an insulator 274 containing an element serving as an impurity is formed in a later step, and a region in the oxide 230 is formed.
  • the interface region between the insulator 224 and the oxide 230 is not reduced in resistance, and thus generation of leakage current can be suppressed.
  • a region 231, a region 232, and a region 234 are formed in the oxide 230.
  • the region 231 and the region 232 are regions obtained by adding impurities to the metal oxide provided as the oxide 230. Note that the region 231 has higher conductivity than at least the region 234.
  • a metal element such as indium or gallium and a dopant that is at least one of the impurities may be added.
  • the dopant an element that forms oxygen vacancies described above, an element that is trapped by oxygen vacancies, or the like may be used.
  • the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • a film containing a dopant may be formed over the region 231 with the insulator 274 as the insulator 274.
  • the insulator 274 an insulating film containing one or more of the above elements is preferably used (see FIG. 10).
  • the insulator 274 including an element that becomes an impurity such as nitrogen is preferably formed over the oxide 230 with the insulator 273 including a metal oxide interposed therebetween.
  • An insulator containing an element that becomes an impurity such as nitrogen may extract and absorb oxygen contained in the oxide 230 in some cases.
  • oxygen vacancies are generated in the region 231 and the region 232.
  • the oxygen vacancies capture an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 274 by the film formation of the insulator 274 or heat treatment after the film formation, so that the regions 231 and 232 have low resistance. Turn into.
  • oxygen vacancies are formed by the added impurity element centering on a region in contact with the insulator 274, and the impurity element further enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. Is done. At that time, it is considered that the impurity is diffused also in the region 232 which is not in contact with the insulator 274, so that the resistance is reduced.
  • the source region and the drain region can be formed in a self-aligned manner by forming the insulator 274. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.
  • an excessive addition of an impurity element such as nitrogen or hydrogen to the oxide 230 can be suppressed.
  • an impurity element such as nitrogen or hydrogen can be contained in the conductor 260, the insulator 252, and the insulator 252. Mixing in the insulator 250 can be prevented.
  • an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260, the insulator 252, and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
  • the insulator 273 and the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, it is preferable to use an ALD method for forming the insulator 273 and the insulator 274 because coverage or density can be increased.
  • a metal oxide film formed using an ALD method can be used as the insulator 273.
  • ALD method a dense thin film can be formed.
  • the metal oxide film preferably contains at least one selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.
  • aluminum oxide is used as the insulator 273.
  • aluminum oxide has a high barrier property and can suppress diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm.
  • Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be increased by increasing the film thickness.
  • the film thickness of the hafnium oxide can be easily controlled, and appropriate addition amounts of hydrogen and nitrogen can be adjusted.
  • silicon nitride, silicon nitride oxide, or silicon oxynitride formed by a CVD method can be used as the insulator 274.
  • silicon nitride oxide is used as the insulator 274.
  • the region 231a and the region 231b preferably have a higher concentration of at least one of hydrogen and nitrogen than the region 234.
  • the concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • the concentration of hydrogen or nitrogen in the region 234 is approximately equal to the vicinity of the center of the region overlapping with the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the insulator 250b of the oxide 230b).
  • the concentration of hydrogen or nitrogen in (part) may be measured.
  • dopant addition methods include ion implantation method in which ionized source gas is added by mass separation, ion doping method in which ionized source gas is added without mass separation, plasma immersion ion implantation method, etc. Can be used.
  • mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
  • mass separation is not performed, high-concentration ions can be added in a short time.
  • an ion doping method in which atomic or molecular clusters are generated and ionized may be used.
  • the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
  • the dopant may be added by plasma treatment.
  • plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, or an ashing apparatus, and a dopant can be added to the region 231 and the region 232.
  • the dopant may be added by an ion doping method through the insulating film 272A.
  • the insulating film 272A is provided to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 270. Therefore, in the direction perpendicular to the top surface of the oxide 230, the thickness of the insulating film 272A differs between the periphery of the insulator 250, the conductor 260, and the insulator 270 and other regions. That is, the thickness of the insulating film 272A is larger in the periphery of the insulator 250, the conductor 260, and the insulator 270 than in the other regions.
  • the region 231 and the region 232 can be provided in a self-aligned manner even in a transistor whose channel length is reduced to about 10 nm to 30 nm.
  • the region 232 may be formed by diffusion of the dopant in the region 231 in a process such as a heat treatment performed in a later process.
  • the region 232 since the region 232 is provided, a high-resistance region is not formed between the region 231 functioning as the source region and the train region and the region 234 where a channel is formed; Can be increased.
  • the region 232 since the region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed.
  • leakage current at the time of non-conduction can be reduced.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the added dopant diffuses into the region 232 of the oxide 230, so that the on-state current can be increased.
  • the insulator 280 is formed over the insulator 274.
  • the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.
  • silicon oxynitride is used as the insulating film.
  • the insulator 280 is preferably formed so that the upper surface has flatness.
  • the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280.
  • the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process.
  • the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.
  • an opening reaching the region 231a of the oxide 230 and an opening reaching the region 231b of the oxide 230 are formed in the insulator 280 and the insulator 274.
  • the opening may be formed using a lithography method. Note that the opening is formed so that the conductor 240a and the conductor 240b are provided in contact with the top surface of the oxide 230.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 240a and the conductor 240b having a flat upper surface can be formed by the conductive film remaining only in the openings (see FIG. 11).
  • a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 3 to 11, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • FIGS. 12A and 13A are top views of a semiconductor device including the transistor 200.
  • FIG. 12B, 12C, 13B, and 13C are cross-sectional views of the semiconductor device.
  • FIG. 12B or FIG. 13B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 12A or FIG. It is also a sectional view in the direction.
  • 12C or 13C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 12A or 13A in the channel width direction of the transistor 200. It is also a sectional view.
  • FIGS. 12A and 13A some elements are omitted for clarity of illustration.
  • the structure of the transistor 200 will be described with reference to FIGS. 12 and 13A, respectively.
  • the material described in detail in ⁇ Structure example of semiconductor device> can be used as the constituent material of the transistor 200.
  • a transistor 200 illustrated in FIG. 12 is different from the semiconductor device illustrated in ⁇ Structure Example of Semiconductor Device> at least in shape of the oxide 230c.
  • the oxide 230c is provided to cover the oxide 230a and the oxide 230b. That is, the oxide 230b is surrounded by the oxide 230a and the oxide 230c. With this structure, entry of impurities into the oxide 230b in which a channel is formed in the region 234 can be suppressed.
  • the side surface of the oxide 230a and the side surface of the oxide 230b are preferably provided so as to be on the same plane.
  • the oxide 230c is preferably formed so as to cover the oxide 230a and the oxide 230b.
  • the oxide 230c is formed in contact with a side surface of the oxide 230a, a top surface and a side surface of the oxide 230b, and a part of the top surface of the insulator 224.
  • the side surfaces of the oxide 230c are located outside the side surfaces of the oxide 230a and the oxide 230b.
  • ⁇ Configuration example of semiconductor device> 14A, 14B, and 14C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a semiconductor device including one capacitor and at least one transistor is referred to as a cell.
  • the conductor 240d is in contact with the conductor 120 that is one of the electrodes of the capacitor 100. Since the conductor 240d can be formed at the same time as the conductor 240a, the process can be shortened.
  • openings are formed in the insulator 214 and the insulator 216.
  • the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed.
  • the opening may be formed by wet etching, but dry etching is preferable for fine processing.
  • an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected.
  • a conductive film to be the conductor 203b and the conductor 209b is formed over the conductive film to be the conductor 203a and the conductor 209a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203b and the conductor 209b.
  • the conductive film to be the conductor 203a and the conductor 209a and the conductive film to be the conductor 203b and the conductor 209b are removed, and the insulator 216 is exposed.
  • the conductive films to be the conductors 203a and 209a and the conductive films to be the conductors 203b and 209b remain only in the openings. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b and the conductor 209 including the conductor 209a and the conductor 209b with a flat upper surface can be formed. Note that part of the insulator 216 may be removed by the CMP treatment.
  • the insulator 220, the insulator 222, and the insulator 224 are formed over the insulator 216, the conductor 203, and the conductor 209.
  • a region 231, a region 232, and a region 234 are formed in the oxide 230.
  • the region 231 and the region 232 are regions obtained by adding impurities to the metal oxide provided as the oxide 230. Note that the region 231 has higher conductivity than at least the region 234.
  • the insulator 280 is formed over the insulator 132 and the conductor 120 (see FIG. 18).
  • the insulator 280 is preferably formed so that the upper surface has flatness.
  • the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280.
  • the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation.
  • a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.
  • a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 15 to 18, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • Each drawing (A) is a top view of a semiconductor device having a cell 600. Further, each drawing (B) and each drawing (C) are cross-sectional views of the semiconductor device. Here, each drawing (B) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in each drawing (A), and is also a cross-sectional view of the cell 600 in the channel length direction. Each drawing (C) is a cross-sectional view taken along the dashed line A3-A4 in each drawing (A), and is a cross-sectional view of the cell 600 in the channel width direction. In the top view of each drawing (A), some elements are omitted for clarity.
  • the cell 600 is different from the semiconductor device shown in ⁇ Structure example of semiconductor device> between at least a conductor 203 functioning as a wiring and a conductor 260 functioning as a first gate electrode.
  • the structure is different from that of the conductor 205. Further, the structure is different in that the conductor 207 is provided between the conductor 209 functioning as a wiring and the conductor 240b functioning as a plug.
  • the conductor 205 is preferably provided so that its length in the channel width direction is larger than that of the region 234 in the oxide 230.
  • the conductor 205 preferably extends in a region where the region 234 of the oxide 230 is outside the end in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.
  • the conductor 207 (the conductor 207a and the conductor 207b) can be formed at the same time as the conductor 205 (the conductor 205a and the conductor 205b).
  • an opening can be provided only in the insulator 220, the insulator 222, and the insulator 224, and the conductor 240b functioning as a plug can be formed. Therefore, productivity can be improved.
  • the cell 600 is different from the semiconductor device described in ⁇ Structure example of semiconductor device> in that a conductor 240 b functioning as a plug is provided in the same layer as the conductor 240 a and the conductor 240 d.
  • the configuration is different.
  • the interface between the insulator 224 and the oxide 230 can be kept clean without being contaminated with a residue or the like generated during processing.
  • the reliability of the semiconductor device can be improved.
  • the cell 600 is different from the semiconductor device described in ⁇ Structure Example of Semiconductor Device> in the shape of the transistor 200.
  • the insulator 130 can serve as the insulator 272 functioning as a side barrier. Therefore, the insulator 272 may not be provided. In this case, the process can be shortened by the amount that the insulator 272 is not formed. In addition, since the insulator 272 is not provided, the region 232 can be formed finely.
  • the cell 600 is different from the semiconductor device described in ⁇ Structure Example of Semiconductor Device> in the shape of the transistor 200.
  • an insulator 275 functioning as a sidewall may be provided instead of the insulator 272 functioning as a side barrier.
  • the insulator 275 preferably has a relatively low dielectric constant. By using a material having a low dielectric constant, parasitic capacitance generated between the conductor 120 and the conductor 260 can be reduced. Thus, the reliability of the semiconductor device can be improved.
  • silicon oxide or the like is formed as the film to be the insulator 275 by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Subsequently, the film to be the insulator 275 can be formed by etching back.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is applied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is supplied to the gate of the transistor 300 (writing).
  • a Low level charge and a High level charge it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given.
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
  • the wiring 1002 takes a potential corresponding to the amount of charge held in the node FG.
  • the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 300 is the case where a low level charge is applied to the gate of the transistor 300 This is because it becomes lower than the apparent threshold voltage Vth_L .
  • the apparent threshold voltage refers to the potential of the wiring 1005 necessary for bringing the transistor 300 into a “conductive state”.
  • the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is in a “conducting state” when the potential of the wiring 1005 is V 0 (> V th_H ). On the other hand, in the case where a low-level charge is supplied to the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the wiring 1005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the wiring 1002, information held in the node FG can be read.
  • the transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • transistor 300 illustrated in FIGS. 25A and 25B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
  • the insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve planarity.
  • the insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
  • TDS temperature programmed desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is 10 ⁇ 10 in terms of the unit amount of the insulator 324 in terms of the amount of desorbed hydrogen molecules in the range of 50 ° C. to 500 ° C. in TDS analysis. 10 15 atom / cm 2 or less, and may be preferably 5 ⁇ 10 15 atom / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 324 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • the insulator 350, the insulator 352, and the insulator 354 are each provided with a conductor 356.
  • the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324.
  • the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen.
  • tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 350 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
  • a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 370.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked.
  • a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
  • the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen.
  • An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
  • the insulator 210 and the insulator 214 are preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. . Therefore, a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be deteriorated. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.
  • the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212 and the insulator 216.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (the conductor 205) included in the transistor 200, and the like.
  • the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300.
  • the conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 200 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.
  • An insulator 280 is provided above the transistor 200.
  • An insulator 282 is provided over the insulator 280.
  • the insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214.
  • the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.
  • An insulator 286 is provided over the insulator 282.
  • the insulator 286 can be formed using a material similar to that of the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.
  • the conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the capacitor element 100 is provided above the transistor 200.
  • the capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.
  • the conductor 112 may be provided over the conductor 246 and the conductor 248.
  • the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 110 has a function as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.
  • indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited to this structure, and a stacked structure of two or more layers may be used.
  • a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • an insulator 130 is provided as a dielectric of the capacitor 100 over the conductor 112 and the conductor 110.
  • the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination
  • the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 100 includes the insulator 130, whereby the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.
  • a conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110.
  • the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.
  • An insulator 150 is provided over the conductor 120 and the insulator 130.
  • the insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.
  • a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • a transistor including an oxide semiconductor with high on-state current can be provided.
  • a transistor including an oxide semiconductor with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a memory device includes the transistor 300, the transistor 200, and the cell 600 including the capacitor 100 as illustrated in FIG.
  • the cell 600 is provided above the transistor 300.
  • a cell 600 is provided above the insulator 216. Note that as the structure of the cell 600, a transistor included in the semiconductor device described in the above embodiment may be used. A cell 600 illustrated in FIG. 26 is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the cell 600 can be easily miniaturized or highly integrated.
  • the process can be shortened.
  • a memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.
  • the memory device illustrated in FIG. 27 is a semiconductor device which forms a memory cell array by arranging the memory devices illustrated in FIG. 25 in a matrix.
  • a memory cell 650a and a memory cell 650b are arranged adjacent to each other.
  • the memory cell 650a and the memory cell 650b each include the transistor 300, the transistor 200, and the capacitor 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006.
  • a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is a node FG.
  • the wiring 1002 is a wiring common to the adjacent memory cells 650a and 650b.
  • a semiconductor device including a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor.
  • miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.
  • a miniaturized or highly integrated semiconductor device can be provided with high productivity.
  • FIG. 29 is a top view of the semiconductor device. Note that in the top view of FIG. 29, some elements are omitted for clarity of illustration.
  • FIG. 28A is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 29 and is also a cross-sectional view of the transistor 200 and the transistor 400 in the channel length direction.
  • FIG. 28B is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 29 and is a cross-sectional view in the channel width direction of the transistor 200.
  • the transistor 200 and the transistor 400 formed over the substrate 201 have different structures.
  • the transistor 400 may have a smaller drain current (Icut) when the back gate potential and the top gate potential are 0 V than the transistor 200.
  • Icut refers to a drain current when the potential of a gate that controls switching operation of a transistor is 0V.
  • the transistor 400 is used as a switching element so that the potential of the back gate of the transistor 200 can be controlled. Accordingly, after the node connected to the back gate of the transistor 200 is set to a desired potential, the transistor 400 is turned off, whereby the charge of the node connected to the back gate of the transistor 200 is prevented from being lost. it can.
  • the conductor, the insulator, and the oxide included in the transistor 400 can be formed in the same step as the conductor, the insulator, and the oxide included in the transistor 200 in the same layer. Therefore, the conductor 405 (the conductor 405a and the conductor 405b) includes the conductor 205 (the conductor 205a and the conductor 205b), the oxide 430 (the oxide 430a1, the oxide 430a2, the oxide 430b1, the oxide 430b2, and The oxide 430c) is the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c), the insulator 450 is the insulator 250, the insulator 452 is the insulator 252, and the conductor 460 (the conductor 460a and the oxide 430c).
  • a conductive film to be the conductor 205a and the conductor 405a is formed.
  • the conductive film to be the conductor 205a and the conductor 405a preferably includes a conductive material having a function of suppressing permeation of oxygen.
  • a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205a and the conductor 405a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when an oxide film to be the oxide 230a, the oxide 430a1, and the oxide 430a2 is formed.
  • the ratio of oxygen contained in the sputtering gas of the oxide film to be the oxide 230a, the oxide 430a1, and the oxide 430a2 is 70% or more, preferably 80% or more, and more preferably 100%.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as hydrogen and water in the oxide film to be the oxide 230a, the oxide 430a1, and the oxide 430a2, and the oxide film to be the oxide 230b, the oxide 430b1, and the oxide 430b2 are removed. And so on.
  • the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • the oxide film that becomes the oxide 230a, the oxide 430a1, and the oxide 430a2, and the oxide film that becomes the oxide 230b, the oxide 430b1, and the oxide 430b2 are processed into island shapes, and the oxide 230a, A stacked structure of the oxide 230b, a stacked structure of the oxide 430a1, and the oxide 430b1, and a stacked structure of the oxide 430a2 and the oxide 430b2 are formed (see FIGS. 30A and 30B). ). Note that part of the insulator 224 may be removed in this step.
  • the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230a and the oxide 230b are preferably substantially perpendicular to the top surface of the insulator 224. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the top surface of the insulator 224, the area of the transistor 200 can be reduced and the density can be increased when the plurality of transistors 200 are provided. .
  • an angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 224 may be an acute angle. In that case, the angle formed between the side surfaces of the oxide 230a and the oxide 230b and the top surface of the insulator 224 is preferably as large as possible.
  • a curved surface is provided between the side surfaces of the oxide 430a1 and the oxide 430b1, the upper surface of the oxide 430b1, the side surfaces of the oxide 430a2 and the oxide 430b2, and the upper surface of the oxide 430b2. That is, it is preferable that the end portions of the side surfaces of the oxide 430b1 and the oxide 430b2 and the end portions of the top surfaces of the oxide 430b1 and the oxide 430b2 are curved.
  • the curvature radius of the curved surface at the end portion of the oxide 430b1 or the oxide 430b2 is 3 nm to 10 nm, preferably 5 nm to 6 nm.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • the oxide film 230C is formed over the stacked structure of the insulator 224, the oxide 230a, and the oxide 230b, the stacked structure of the oxide 430a1, and the oxide 430b1, and the stacked structure of the oxide 430a2 and the oxide 430b2. (See FIGS. 30C and 30D).
  • the oxide film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using the same conditions as those for forming the oxide film 230a. Alternatively, the oxide film 230C may be formed using the same conditions as those for the oxide film 230b. A film may be formed. Further, a film may be formed by combining these conditions.
  • the oxide film 230C is formed by a method similar to that for forming the oxide 230a, the oxide 430a1, and the oxide 430a2, in accordance with characteristics required for the oxide 230c and the oxide film to be the oxide 430c, or A deposition method similar to that of the oxide film to be the oxide 230b, the oxide 430b1, and the oxide 430b2 may be used.
  • the oxide film 230C is processed into an island shape, so that the oxide 230 including the oxide 230c and the oxide 430c are formed (see FIGS. 31A and 31B).
  • 230c is preferably formed to cover the oxide 230a and the oxide 230b.
  • the oxide 430c is preferably formed to cover the oxide 430a1, the oxide 430b1, the oxide 430a2, and the oxide 430b2.
  • the processing may be performed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing.
  • a hard mask may be used instead of the resist mask.
  • the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed (see FIGS. 31C and 31D).
  • the description of each of the above embodiments can be referred to.
  • the insulating film 271A is etched to form an insulator 271 and an insulator 471.
  • the insulator 271 and the insulator 471 function as a hard mask.
  • the side surface of the insulator 452, the side surface of the conductor 460a, the side surface of the conductor 460b, and the side surface of the insulator 470 can be formed substantially perpendicular to the top surface of the substrate.
  • the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched, and the insulator 250, the insulator 252 and the conductor 260 (conductor) 260a and the conductor 260b) and the insulator 270, and the insulator 450, the insulator 452, the conductor 460 (the conductor 460a and the conductor 460b), and the insulator 470 are formed (FIG. 32A). And FIG. 32 (B)).
  • the etching removes part of the oxide 230c and the oxide 430c in a region where the oxide 230c and the insulator 250 do not overlap and a region where the oxide 430c and the insulator 450 do not overlap. May be.
  • the thickness of the region of the oxide 230c that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
  • the thickness of the region where the oxide 430 c overlaps with the insulator 450 may be larger than the thickness of a region where the oxide 430 c does not overlap with the insulator 450.
  • the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are preferably in the same plane.
  • the side surface of the insulator 450, the side surface of the insulator 452, the side surface of the conductor 460a, the side surface of the conductor 460b, and the side surface of the insulator 470 are preferably in the same plane.
  • the post-process may be performed without removing the hard mask (the insulator 271 and the insulator 471) even after the above processing.
  • a region 231, a region 232, and a region 234 are formed in the oxide 230.
  • a low resistance region is selectively formed also in the oxide 430.
  • the region 232 In order to add an impurity to the region 231, the region 232, and part of the oxide 430, for example, a metal element such as indium or gallium and a dopant that is at least one of the impurities may be added.
  • a metal element such as indium or gallium and a dopant that is at least one of the impurities may be added.
  • the dopant the elements described in the above embodiments can be used.
  • a film containing a dopant may be formed as the insulator 274 over the region 231 with the insulator 273 interposed therebetween.
  • a film containing a dopant may be formed as the insulator 274 over the region 231 with the insulator 273 interposed therebetween.
  • an insulating film containing one or more of the above elements is preferably used.
  • the insulator 273 and the insulator 274 are formed so as to cover the insulator 471 (see FIGS. 32C and 32D).
  • the insulator 274 including an element that becomes an impurity such as nitrogen is preferably formed over the oxide 230 and the oxide 430 with the insulator 273 including a metal oxide interposed therebetween.
  • An insulator including an element that becomes an impurity such as nitrogen might extract and absorb oxygen contained in the oxide 230 and the oxide 430 in some cases.
  • oxygen vacancies are generated in the region 231 and the region 232.
  • the oxygen vacancies capture an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 274 by the film formation of the insulator 274 or heat treatment after the film formation, so that the regions 231 and 232 have low resistance. Turn into.
  • oxygen deficiency is formed by the added impurity element centering on a region in contact with the insulator 274, and the impurity element enters oxygen deficiency, so that the carrier density is high.
  • the resistance is reduced.
  • the impurity diffuses also in the region 232 that is not in contact with the insulator 274, so that the resistance is reduced.
  • an impurity element such as nitrogen or hydrogen is excessively added to the oxide 230 and the oxide 430. It can suppress adding.
  • an impurity element such as nitrogen or hydrogen is added to the conductor 260, the insulator 252, and the insulator 250. Mixing can be prevented.
  • an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260, the insulator 252, and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
  • an insulating film to be the insulator 280 is formed over the insulator 274.
  • an insulator 282 is formed over the insulator 280.
  • the insulator 282 is preferably formed with a sputtering apparatus. For example, when aluminum oxide having a barrier property is used for the insulator 282, diffusion of impurities from the structure formed above the insulator 282 to the transistor 200 and the transistor 400 can be suppressed.
  • an insulator 286 is formed over the insulator 282.
  • an insulator containing oxygen such as a silicon oxide film or a silicon oxynitride film is formed by a CVD method.
  • the insulator 286 preferably has a lower dielectric constant than the insulator 282.
  • an opening reaching the transistor 200, the transistor 400, the wiring, and the like is formed in the insulator 286, the insulator 282, and the insulator 280.
  • a conductive film to be the conductor 240 and the conductor 440 is formed.
  • the conductor 240 and the conductive film to be the conductor 440 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 240 and the conductive film to be the conductor 440 are formed so as to fill an opening formed by the insulator 280 and the like. Therefore, it is preferable to use the CVD method (particularly the MOCVD method).
  • the conductive film to be the conductor 240 and the conductor 440 may have a stacked structure of titanium nitride and tungsten.
  • the conductor 240 and the conductor 440 are removed by removing part of the conductor 240 and the conductive film to be the conductor 440 until the insulator 286 is exposed by an etch-back process or a CMP process. Form.
  • the insulator 286 can also be used as a stopper layer, and the insulator 286 may be thin.
  • the conductor 112 and a conductive film to be the conductor 110 are formed over the insulator 286.
  • the conductor 112 and the conductive film to be the conductor 110 include, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or an alloy containing the above-described metal as a component, It can be formed using an alloy or the like combining the above metals.
  • a metal selected from one or more of manganese and zirconium may be used.
  • a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a two-layer structure in which a titanium film is stacked on an aluminum film a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, a tantalum nitride film, or a tungsten nitride film
  • a two-layer structure in which a tungsten film is stacked thereon, a titanium film, and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon Alternatively, an alloy film or a nitride film in which one or more metals selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.
  • the conductor 112 and the conductor 110 are formed by etching the conductor 112 and the conductive film to be the conductor 110.
  • the etching process as an over-etching process, part of the insulator 286 may be removed at the same time.
  • the insulator 112 covering the conductor 112 and the side and upper surfaces of the conductor 110 is formed.
  • the insulator 130 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like is used. What is necessary is just to provide by lamination or a single layer.
  • a stacked structure of a high-k material such as aluminum oxide and a material with high dielectric strength such as silicon oxynitride is preferable.
  • the capacitor 100 can secure a sufficient capacity with the high-k material and the insulation resistance is improved, so that electrostatic breakdown of the capacitor 100 can be suppressed and the reliability of the capacitor 100 can be improved. it can.
  • a conductive film to be the conductor 120 is formed over the insulator 130.
  • the conductive film to be the conductor 120 can be formed using a material and a method similar to those of the conductor 110.
  • unnecessary portions of the conductive film to be the conductor 120 are removed by etching.
  • the conductor 120 is formed by removing the resist mask.
  • the conductor 120 is preferably provided so as to cover the side surface and the upper surface of the conductor 110 with the insulator 130 interposed therebetween. With this configuration, the side surface of the conductor 110 faces the conductor 120 with the insulator 130 interposed therebetween. Therefore, in the capacitor 100, the sum of the upper surface and the side surface of the conductor 110 functions as a capacitor, so that a capacitor with a large capacitance per projected area can be formed.
  • an insulator 150 that covers the capacitor 100 is formed (see FIG. 28).
  • the insulator to be the insulator 150 can be formed using a material and a method similar to those of the insulator 286 and the like.
  • a semiconductor device including the capacitor 100, the transistor 200, and the transistor 400 can be manufactured. As illustrated in FIGS. 30 to 32, the capacitor 100, the transistor 200, and the transistor 400 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • ⁇ Modification of semiconductor device> A modification example of the transistor described in this embodiment will be described below with reference to FIGS. Note that in the semiconductor device illustrated in FIGS. 34A and 34B, structures having the same functions as the structures forming the semiconductor device illustrated in ⁇ Example of Structure of Semiconductor Device> are denoted by the same reference numerals. Also in this item, as the constituent material of the semiconductor device, the material described in detail in ⁇ Constituent material of the semiconductor device> can be used.
  • a transistor 200 and a transistor 400 illustrated in FIGS. 34A and 34B are different from the semiconductor device illustrated in ⁇ Structure Example of Semiconductor Device> in that at least an insulator 272 and an insulator 472 are included.
  • the insulator 272 functioning as a barrier film is provided in contact with the side surfaces of the insulator 250, the insulator 252, the conductor 260, and the insulator 270.
  • the insulator 472 functioning as a barrier film is provided in contact with side surfaces of the insulator 450, the insulator 452, the conductor 460, and the insulator 470.
  • the insulator 272 and the insulator 472 may be formed using an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen.
  • an insulating material having a function of suppressing transmission of impurities such as water or hydrogen and oxygen.
  • aluminum oxide or hafnium oxide is preferably used. Accordingly, oxygen in the insulator 250, the insulator 252, and the insulator 450 and the insulator 452 can be prevented from diffusing to the outside.
  • impurities such as hydrogen and water are mixed into the region 234 of the oxide 230 and the channel formation region of the oxide 430 from the end portions of the insulator 250 and the insulator 252, and the insulator 450 and the insulator 452. Can be suppressed.
  • the insulator has a function of suppressing transmission of impurities such as water or hydrogen and oxygen, and the side surface of the insulator 250, the side surface of the insulator 252, and the conductor 260 And the side surface of the insulator 450, the side surface of the insulator 452, and the side surface of the conductor 460 can be covered. Accordingly, a range in which the region 232 of the oxide 230 and the region where the resistance of the oxide 430 is reduced can be appropriately adjusted.
  • a transistor when a transistor is miniaturized and a channel length is formed to be about 10 nm to 30 nm, an impurity element contained in a structure provided around the transistor 200 is diffused into the region 234, so that the region 231a and the region 231b There is a risk of electrical conduction.
  • the first gate potential is 0 V, the source region and the drain region can be prevented from being electrically connected.
  • a semiconductor device illustrated in FIG. 35 is a memory device including the transistor 400, the transistor 300, the transistor 200, and the capacitor 100.
  • the transistor 400 the transistor 400, the transistor 300, the transistor 200, and the capacitor 100.
  • the transistor 200 is a transistor including a metal oxide in a channel formation region, and any of the transistors described in the above embodiments can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • a memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.
  • capacitor 100 the capacitor 100, the transistor 200, the transistor 300, and the transistor 400
  • the capacitor and the transistor included in the semiconductor device described in the above embodiment may be used.
  • the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 35A and 35B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • an insulator 280, an insulator 274, an insulator 273, an insulator 224, and an insulator in the vicinity of a region overlapping with a dicing line provided on the outer edge of the memory cell including the transistor 200 or the transistor 400 222, the insulator 220, the insulator 216, the insulator 214, and the insulator 212 are provided with openings that reach the insulator 210.
  • the insulator 280, the insulator 274, the insulator 273, the insulator 224, the insulator 222, the insulator 220, the insulator 216, the side surfaces of the insulator 214 and the insulator 212, and the bottom surface of the insulator 210 are covered.
  • An insulator 282 is provided.
  • the insulator 210 and the insulator 282 are in contact with each other in the opening.
  • the adhesiveness can be improved by forming the insulator 210 and the insulator 282 using the same material and the same method.
  • aluminum oxide can be used.
  • the insulator 214, the transistor 200, and the transistor 400 can be wrapped with the insulator 214 and the insulator 282. Since the insulator 360, the insulator 222, and the insulator 282 have a function of suppressing diffusion of oxygen, hydrogen, and water, a substrate is provided for each circuit region in which the semiconductor element described in this embodiment is formed. Thus, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed into the transistor 200 or the transistor 400 from the side surface direction of the divided substrate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • 2T type, 3T type a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied.
  • the OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 36 shows a configuration example of NOSRAM.
  • a NOSRAM 1600 illustrated in FIG. 36 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
  • the memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a word ship RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • one memory cell 1611 stores 3-bit (eight values) data.
  • the controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0].
  • the controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to be accessed.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • the column driver 1660 drives the source line SL and the bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
  • FIG. 37A is a circuit diagram illustrating a configuration example of the memory cell 1611.
  • the memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, the word line RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor.
  • the capacitor C61 is a storage capacitor for holding the potential of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • a memory cell 1612 shown in FIG. 37C is a modification example of the memory cell 1611 and is obtained by changing a reading transistor to an n-channel transistor (MN61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • a memory cell 1613 illustrated in FIG. 37D is a 3T gain cell, and is electrically connected to the word line WWL, the word line RWL, the bit line WBL, the bit line RBL, the source line SL, the wiring BGL, and the wiring PCL. Yes.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • the OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.
  • the NOSRAM 1600 Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
  • the transistor 200 is used as the OS transistor MO61 and the OS transistor MO62
  • the capacitor is used as the capacitor C61 and the capacitor C62.
  • the transistor 300 can be used as the transistor MP61 and the transistor MN62. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • DOSRAM is described with reference to FIGS. 38 and 39 as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention.
  • DOSRAM registered trademark
  • a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention.
  • DOSRAM registered trademark
  • 1T transistor
  • 1C capacitor
  • OS memory is applied to DOSRAM as well as NOSRAM.
  • FIG. 38 shows a configuration example of the DOSRAM.
  • the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
  • MC-SA array 1420 a sense amplifier array 1420
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a global bit line GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • the global bit line GBLL and the global bit line GBLR are stacked on the memory cell array 1422.
  • a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
  • the memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> to 1425 ⁇ N-1>.
  • FIG. 39A shows a configuration example of the local memory cell array 1425.
  • the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, and a bit line BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 39B illustrates a circuit configuration example of the memory cell 1445.
  • the memory cell 1445 includes a transistor MW1, a capacitor CS1, a terminal B1, and a terminal B2.
  • the transistor MW1 has a function of controlling charging / discharging of the capacitor CS1.
  • the gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitor.
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant potential (for example, a low power supply potential) is input to the terminal B2.
  • the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1.
  • the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated.
  • the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • the transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, Vth of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage at the terminal B1 may be a fixed potential (for example, a negative constant potential), or the voltage at the terminal B1 may be changed in accordance with the operation of the DOSRAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.
  • the sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> to 1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to the sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference between the bit line pair, and a function of holding this potential difference.
  • the switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
  • bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier.
  • a global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form one bit line pair.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
  • the controller 1405 has a function of controlling the overall operation of the DOSRAM 1400.
  • the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of decoding an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
  • a column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column.
  • the switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413.
  • the plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
  • the column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • the global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference.
  • Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.
  • Data is written to the global bit line pair by the input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
  • the PRS 3133 [0] is active.
  • the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
  • the OS transistor MO32 of the memory circuit 3137 is a source follower, and therefore the gate potential of the Si transistor M31 is increased by boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
  • the CM 3135 also has a multiplexer function.
  • FIG. 42 shows a configuration example of the PLE 3121.
  • the PLE 3121 includes an LUT (Look Up Table) block 3123, a register block 3124, a selector 3125, and a CM 3126.
  • the LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the inputs inA-inD.
  • the selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
  • the PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
  • the register block 3124 is configured by a nonvolatile register.
  • a nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.
  • the register block 3124 includes OS-FF 3140 [1] and OS-FF 3140 [2].
  • the signal user_res, the signal load, and the signal store are input to the OS-FF 3140 [1] and the OS-FF 3140 [2].
  • the clock signal CLK1 is input to the OS-FF 3140 [1]
  • the clock signal CLK2 is input to the OS-FF 3140 [2].
  • FIG. 43A illustrates a configuration example of the OS-FF 3140.
  • the shadow register 3142 functions as a backup circuit for the FF 3141.
  • the shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
  • the shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, an Si transistor M37, an Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B.
  • the memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133.
  • the memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36.
  • the memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36.
  • the nodes N36 and NB36 are the gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes.
  • the nodes N37 and NB37 are the gates of the Si transistor M37 and the Si transistor MB37.
  • the transistor 200 can be used as the OS transistor MO35 and the OS transistor MOB35, and the capacitor 100 can be used as the capacitor C36 and the capacitor CB36. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021.
  • the DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • the input data may exceed 1000.
  • the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions.
  • the DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.
  • a NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can reduce the area of the memory compared to the FPGA configured with SRAM. Therefore, even if a context switching function is added, the area increase is small.
  • the OS-FPGA can transmit data and parameters at high speed by boosting.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed.
  • the PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog calculation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.
  • Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.
  • the AI system 4041 includes an audio codec 4032 and a video codec 4033.
  • the audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy.
  • circuit design for separating data writing and reading becomes complicated.
  • the analog arithmetic circuit 4011 may use MRAM as an analog memory.
  • MRAM has a low resistance change rate and has a problem in terms of storage accuracy.
  • the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.
  • FIG. 45A shows an AI system 4041A in which the AI systems 4041 described in FIG. 44 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.
  • An AI system 4041A illustrated in FIG. 45A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number).
  • the AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.
  • FIG. 45B shows an AI system 4041B in which the AI system 4041 described in FIG. 44 is arranged in parallel as in FIG. 45A, and signals can be transmitted and received between systems via a network. is there.
  • An AI system 4041B illustrated in FIG. 45B includes a plurality of AI systems 4041_1 to 4041_n.
  • the AI systems 4041_1 to 4041_n are connected to each other via a network 4099.
  • the network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
  • the communication module can communicate via an antenna.
  • An antenna For example, Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Camper Area Network, MAN (Metropore Network), MAN (Metropore Network), which are the foundations of the World Wide Web (WWW).
  • Each electronic device can be connected to a computer network such as Area Network) or GAN (Global Area Network) to perform communication.
  • LTE Long Term Evolution
  • GSM Global System for Mobile Communication: registered trademark
  • EDGE Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Equation
  • Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.
  • analog signals obtained by an external sensor or the like can be processed by separate AI systems.
  • information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information
  • various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor
  • analog signals can be processed by separate AI systems. it can.
  • the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.
  • the AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.
  • FIG. 46 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 shown in FIG. 46 includes a lead 7001 and a circuit portion 7003.
  • the AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004).
  • the circuit portion 7003 is provided with the various circuits described in the above embodiment in one die.
  • the circuit portion 7003 has a stacked structure as shown in FIG. 25 in the above embodiment, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.
  • QFP Quad Flat Package
  • FIG. 47A is an external view illustrating an example of an automobile.
  • the automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.
  • the automobile 2980 includes an antenna, a battery, and the like.
  • An information terminal 2910 illustrated in FIG. 47B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
  • the display portion 2912 includes a display panel using a flexible substrate and a touch screen.
  • the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
  • the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
  • a laptop personal computer 2920 illustrated in FIG. 47C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
  • the laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
  • FIG. 47E illustrates an example of a bangle information terminal.
  • the information terminal 2950 includes a housing 2951, a display portion 2952, and the like.
  • the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951.
  • the display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.
  • the display surface of the display portion 2962 is curved, and display can be performed along the curved display surface.
  • the display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like.
  • an application can be started by touching an icon 2967 displayed on the display unit 2962.
  • the operation switch 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release in addition to time setting. .
  • the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.
  • Vg-Id characteristics electrical characteristics of the transistor 200 according to one embodiment of the present invention were measured, and the effects described in the above embodiments were verified. The results are shown below.
  • Samples used in this example are a sample A that does not have the insulator 273, a sample B in which a silicon oxide film having a thickness of 1 nm is formed by the ALD method as the insulator 273, and a thickness that is formed by the ALD method as the insulator 273.
  • Sample C There are three types of Sample C, in which a 1 nm aluminum oxide film is formed. The three samples are standardized under the same manufacturing conditions (details are described in the previous embodiment) except for the condition of the insulator 273 described above.
  • FIG. 48 the Vg-Id measurement result of each sample is shown. In each sample, the Vg-Id curves of the six transistors that were measured are overwritten.
  • the transistor B includes the insulator 273 between the oxide 230 and the insulator 274.
  • the transistor B did not achieve on / off characteristics as compared with the transistor B.
  • the effect of introducing the insulator 273 was to control hydrogenation from the insulator 274 to the oxide 230, but in this example, the opposite result was obtained. became. Since on / off characteristics are not obtained in all measurement elements, the use of silicon oxide having a thickness of 1 nm formed by the ALD method for the insulator 273 may promote the reduction in resistance of the oxide 230. is there.

Landscapes

  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur qui est microfabriqué et hautement intégré. La présente invention comprend : un semi-conducteur à oxyde ayant une première région, une deuxième région et une troisième région adjacente à la première région et à la deuxième région ; un premier corps isolant sur le semi-conducteur à oxyde ; un corps conducteur sur le premier corps isolant ; un deuxième corps isolant sur le semi-conducteur à oxyde, sur le premier corps isolant et sur le corps conducteur ; et un troisième corps isolant sur le deuxième corps isolant. La première région est en contact avec le premier corps isolant, et chevauche le troisième corps isolant par l'intermédiaire du premier corps isolant et du corps conducteur. La deuxième région est en contact avec le deuxième corps isolant, et chevauche le troisième corps isolant par l'intermédiaire du deuxième corps isolant. Le deuxième corps isolant est constitué d'un oxyde métallique. Le troisième corps isolant contient de l'hydrogène ou de l'azote.
PCT/IB2018/051416 2017-03-13 2018-03-06 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur WO2018167601A1 (fr)

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