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WO2018163012A1 - Dispositif à semi-conducteur et procédé de fabrication d'un dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication d'un dispositif à semi-conducteur Download PDF

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Publication number
WO2018163012A1
WO2018163012A1 PCT/IB2018/051210 IB2018051210W WO2018163012A1 WO 2018163012 A1 WO2018163012 A1 WO 2018163012A1 IB 2018051210 W IB2018051210 W IB 2018051210W WO 2018163012 A1 WO2018163012 A1 WO 2018163012A1
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Prior art keywords
insulator
oxide
region
conductor
transistor
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PCT/IB2018/051210
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English (en)
Japanese (ja)
Inventor
山崎舜平
及川欣聡
奥野直樹
安藤元晴
岡本悟
Original Assignee
株式会社半導体エネルギー研究所
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Publication of WO2018163012A1 publication Critical patent/WO2018163012A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Integrated Circuit Integrated Circuit: IC
  • LSI and VLSI technologies that have higher integration ICs are used.
  • Such an IC is mounted on a circuit board, for example, a printed wiring board, and is used as one of components of various electronic devices constituting a computer, an information terminal, a display device, an automobile, and the like.
  • AI artificial intelligence
  • desktop computers As computers and information terminals, desktop computers, laptop computers, tablet computers, smartphones, mobile phones and the like are known.
  • Silicon-based semiconductor materials are widely known as semiconductor materials used for semiconductor elements, but oxide semiconductors have attracted attention as other materials.
  • a transistor using an oxide semiconductor has extremely small leakage current in a non-conduction state.
  • a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
  • An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Another object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. Another object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • One embodiment of the present invention includes an oxide, an insulator, and a conductor which sandwiches the insulator and overlaps with the first region of the oxide, and the oxide includes In, the element M (M Includes Al, Ga, Y, or Sn) and Zn, and the oxide has a second region adjacent to the first region, and the concentration of the element M in the second region is This is a semiconductor device having a concentration higher than that of the element M in the region.
  • An oxide a first insulator over the oxide, a second insulator adjacent to a side surface of the first insulator, and a first region of oxide sandwiched between the first insulator and And the oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn, and the oxide is adjacent to the first region.
  • the second region has a region overlapping with the second insulator, and the concentration of the element M in the second region is higher than the concentration of the element M in the first region. is there.
  • the oxide may further include a third region, and the third region is preferably adjacent to the second region.
  • the concentration of the element M in the second region is preferably larger than the concentration of the element M in the first region and the concentration of the element M in the third region.
  • the carrier density of the first region is preferably lower than the carrier density of the second region, and the carrier density of the second region is preferably lower than the third carrier density.
  • the element M is preferably Ga.
  • a first mask and a second mask are formed over an oxide containing In, the element M (M is Al, Ga, Y, or Sn), and Zn, and the oxide
  • the addition of the element M is preferably performed using one or a plurality of methods selected from an ion implantation method, an ion doping method, a plasma treatment, and a plasma immersion ion implantation method.
  • the element M is preferably Ga.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device in which fluctuation in electrical characteristics is suppressed, stable electrical characteristics, and reliability is improved can be provided.
  • a semiconductor device capable of holding data for a long period can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a novel semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a highly productive semiconductor device can be provided.
  • a semiconductor device with a high degree of design freedom can be provided.
  • a semiconductor device that can reduce power consumption can be provided.
  • a semiconductor device in which a manufacturing process is simplified and a manufacturing method thereof can be provided. Further, according to one embodiment of the present invention, a semiconductor device with a reduced area and a manufacturing method thereof can be provided.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a cross-sectional view of a semiconductor device according to one embodiment of the present invention and a graph showing a concentration distribution of a metal element.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device.
  • FIG. 1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • a top view also referred to as a “plan view”
  • a perspective view a perspective view, and the like
  • some components may not be described in order to facilitate understanding of the invention.
  • description of some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows between the source and drain via the channel region.
  • a channel region refers to a region through which a current mainly flows.
  • the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or in a region where a channel is formed This is the length of the part.
  • the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor).
  • channel width Sometimes referred to as “channel width”).
  • the effective channel width may be larger than the apparent channel width, and the influence may not be negligible.
  • the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
  • the apparent channel width may be referred to as “surrounded channel width (SCW)”.
  • SCW surrounded channel width
  • channel width in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease.
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by mixing impurities.
  • impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • a silicon oxynitride film has a higher oxygen content than nitrogen in its composition.
  • oxygen is 55 atomic% to 65 atomic%
  • nitrogen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • the silicon nitride oxide film has a nitrogen content higher than that of oxygen.
  • nitrogen is 55 atomic% to 65 atomic%
  • oxygen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • the terms “film” and “layer” can be interchanged with each other.
  • the term “conductive layer” may be changed to the term “conductive film”.
  • the term “insulating film” may be changed to the term “insulating layer” in some cases.
  • the term “insulator” can be restated as an insulating film or an insulating layer.
  • the term “conductor” can be restated as a conductive film or a conductive layer.
  • the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
  • the transistors described in this specification and the like are field-effect transistors unless otherwise specified.
  • the transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.
  • a metal oxide is a metal oxide in a broad expression.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as OS FET, it can be translated into a transistor including an oxide or an oxide semiconductor.
  • ⁇ Configuration Example 1 of Semiconductor Device> 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention.
  • FIG. 1A is a top view of the transistor 200.
  • 1B, 1C, and 1D are cross-sectional views of the transistor 200.
  • FIG. 1B is a cross-sectional view taken along dashed-dotted line AB in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view taken along dashed-dotted line CD in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view taken along the dashed line EF in FIG. In the top view of FIG. 1A, some elements are omitted for clarity.
  • the transistor 200 includes an insulator 214 and an insulator 216 which are disposed over a substrate (not shown), and a conductor 205 which is disposed so as to be embedded in the insulator 214 and the insulator 216.
  • An insulator 220 disposed on the insulator 216 and the conductor 205, an insulator 222 disposed on the insulator 220, an insulator 224 disposed on the insulator 222, and an insulator Oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on 224, insulator 250 disposed on oxide 230, and conductive disposed on insulator 250.
  • a body 260 (conductor 260a and conductor 260b), an insulator 272 arranged to be in contact with at least the side surface of insulator 250 and to cover conductor 260, oxide 230, and Having an insulator 274 arranged in contact with Entai 272, a.
  • the transistor 200 has a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are stacked as illustrated in FIG. 1, but the present invention is not limited thereto.
  • a two-layer structure of the oxide 230a and the oxide 230b or a stacked structure of four or more layers may be used.
  • a single layer including only the oxide 230b or only the oxide 230b and the oxide 230c may be provided.
  • the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this.
  • a single layer or a stacked structure of three or more layers may be used.
  • FIG. 1B An enlarged view of a region 239 in the vicinity of the channel surrounded by a broken line in FIG. 1B is shown in FIG.
  • the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200 and a region 231 functioning as a source region or a drain region (region 231a and region). 231b) and a region 232 (region 232a and region 232b).
  • the region 231 functioning as a source region or a drain region is a region with high carrier density and low resistance.
  • the region 234 functioning as a channel formation region is a region having a lower carrier density than the region 231 functioning as a source region or a drain region.
  • the region 232 is a region that suppresses permeation of hydrogen and oxygen in the oxide 230. By providing such a region, mixing of hydrogen from the region 231 to the region 234 can be suppressed, and oxygen diffusion from the region 234 to the region 231 can be suppressed.
  • the region that suppresses the permeation of hydrogen or oxygen is the concentration of the element 230 when the oxide 230 is an In—M—Zn oxide containing indium, the element M, and zinc. Can be provided by increasing the height.
  • the element applicable to the element M include aluminum, gallium, yttrium, and tin.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • FIG. 5B is a diagram showing the gallium concentration (Ga concentration) in each region when gallium is used as the element M.
  • the gallium concentration in the region 232 is higher than the gallium concentrations in the region 231 and the region 234. By increasing the gallium concentration in the region 232, the region 232 can be a region in which permeation of hydrogen or oxygen is suppressed.
  • the length of the region 234 in the channel length direction is about 5 nm to 300 nm
  • the length of the region 232a and the region 232b in the channel length direction is preferably 0.1 nm to 100 nm, and preferably 1 nm to 10 nm. It is more preferable to make it below.
  • the region 234 can have a higher oxygen concentration and a lower hydrogen concentration than the region 231. Moreover, this state can be maintained over a long period of time.
  • a highly reliable semiconductor device having favorable electric characteristics can be obtained.
  • the region 232 does not overlap with the conductor 260 functioning as a gate electrode; however, this embodiment is not limited thereto.
  • the region 232 may overlap with the conductor 260 functioning as a gate electrode and may function as a so-called overlap region (also referred to as a Lov region).
  • the region 231 is preferably in contact with the insulator 274.
  • the region 231 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 232 and the region 234.
  • the region 232 has a region overlapping with the insulator 272.
  • the region 232 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 234.
  • a metal element such as indium and an impurity element such as hydrogen and nitrogen
  • the region 232 can have a lower carrier density than the region 231 functioning as a source region or a drain region and a higher carrier density than the region 234 functioning as a channel formation region.
  • the region 232 functions as a junction region between the channel formation region and the source region or the drain region.
  • a high resistance region is not formed between the region 231 functioning as a source region or a drain region and the region 234 functioning as a channel formation region, so that the on-state current of the transistor can be increased. ,preferable.
  • the region 234 overlaps with the conductor 260.
  • the region 234 is disposed between the region 232 a and the region 232 b, and at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen is lower than that of the region 231 and the region 232. It is preferable.
  • the boundary between the region 231, the region 232, and the region 234 may not be clearly detected.
  • Concentrations of metal elements such as indium and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). You may do it. In other words, the closer to the region 234 from the region 231 to the region 232, the lower the concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen.
  • the region 234, the region 231, and the region 232 are formed in the oxide 230a, the oxide 230b, and the oxide 230c, but the present invention is not limited thereto. And at least the oxide 230b may be formed. For example, these regions may be formed only in the oxide 230b and the oxide 230c. Further, in the figure, the boundary of each region is displayed substantially perpendicular to the interface between the insulator 224 and the oxide 230, but this embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 in the vicinity of the surface of the oxide 230b and recede toward the conductor 252a or the conductor 252b in the vicinity of the lower surface of the oxide 230b.
  • the oxide 230 is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • a transistor including an oxide semiconductor its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including an oxide semiconductor in which an oxygen vacancy is included in a channel formation region is likely to be normally on. For this reason, it is preferable that oxygen vacancies in the channel formation region be reduced as much as possible.
  • the insulator 250 overlapping with the region 234 of the oxide 230 preferably contains more oxygen than oxygen (also referred to as excess oxygen) that satisfies the stoichiometric composition. That is, excess oxygen in the insulator 250 diffuses into the region 234, so that oxygen vacancies in the region 234 can be reduced.
  • the insulator 272 is preferably provided in contact with the insulator 250.
  • the insulator 272 preferably has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits). Since the insulator 272 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side.
  • the region 232 is provided adjacent to the region 234, mixing of hydrogen from the region 231 into the region 234 and diffusion of oxygen supplied to the region 234 in the direction of the region 231 can be suppressed. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.
  • the transistor 200 is preferably covered with an insulator 274 having a barrier property to prevent entry of impurities such as water or hydrogen.
  • An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. Insulators using an insulating material that has (which is difficult to transmit the above impurities).
  • the conductor 260 may function as a first gate electrode.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be substantially shifted to the positive side. Further, when the threshold value of the transistor 200 is set higher than 0 V, off-state current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260 is 0 V can be reduced.
  • the conductor 205 functioning as the second gate electrode is provided so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided so that its length in the channel width direction is larger than that of the region 234 in the oxide 230.
  • the conductor 205 preferably extends in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.
  • the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.
  • a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • a conductor 205a is formed in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and a conductor 205b is formed further inside.
  • the heights of the upper surfaces of the conductors 205a and 205b and the height of the upper surface of the insulator 216 can be approximately the same.
  • the transistor 200 has a structure in which the conductors 205a and 205b are stacked, the present invention is not limited to this. For example, only the conductor 205b may be provided.
  • the conductor 205a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom.
  • impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom.
  • a conductive material that has a function of suppressing diffusion of at least one of oxygen for example, oxygen atoms and oxygen molecules
  • the oxygen is difficult to transmit.
  • the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.
  • the conductor 205a When the conductor 205a has a function of suppressing diffusion of oxygen, the conductivity can be prevented from being reduced due to oxidation of the conductor 205b.
  • a conductive material having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductor 205a may be a single layer or a stack of the above conductive materials. Thus, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side through the conductor 205 from the insulator 214 can be suppressed.
  • the conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above-described conductive material.
  • the insulator 214 preferably functions as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor from the substrate side. Therefore, the insulator 214 has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N 2 O, NO, NO 2, and the like) and a copper atom. It is preferable to use an insulating material (which is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).
  • oxygen for example, oxygen atoms and oxygen molecules
  • the insulator 214 aluminum oxide, silicon nitride, or the like is preferably used.
  • impurities such as hydrogen and water can be prevented from diffusing from the insulator 214 to the transistor side.
  • diffusion of oxygen contained in the insulator 224 and the like to the substrate side from the insulator 214 can be suppressed.
  • the insulator 216 functioning as an interlayer film preferably has a lower dielectric constant than the insulator 214.
  • parasitic capacitance generated between the wirings can be reduced.
  • the insulator 216 functioning as an interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3) ) Or an insulator such as (Ba, Sr) TiO 3 (BST) can be used in a single layer or stacked layers.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220, the insulator 222, and the insulator 224 function as gate insulators.
  • an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used as the insulator 224 in contact with the oxide 230. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the oxide film has a thickness of 0.0 ⁇ 10 20 atoms / cm 3 or more.
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Is preferred.
  • the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side.
  • the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.
  • the insulator 222 is so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. By using a high-k material for the insulator that functions as a gate insulator, transistors can be miniaturized and highly integrated. In particular, it is preferable to use an insulating material such as aluminum oxide and hafnium oxide that has a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits). In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining with an insulator of a high-k material.
  • the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient. Further, although the structure in which the insulator 220, the insulator 222, and the insulator 224 function as gate insulators in the transistor 200 is described, this embodiment is not limited thereto. For example, any two layers or one layer of the insulator 220, the insulator 222, and the insulator 224 may be provided as the gate insulator.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230 includes a region 231, a region 232, and a region 234.
  • at least part of the region 231 is preferably in contact with the insulator 274.
  • at least part of the region 231 preferably has a concentration of at least one of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.
  • the region 231a or the region 231b functions as a source region or a drain region.
  • at least part of the region 234 functions as a region where a channel is formed.
  • the oxide 230 preferably includes a region 232.
  • the region 232 is a junction region, the on-state current can be increased and the leakage current (off-state current) during non-conduction can be reduced.
  • the oxide 230b is provided over the oxide 230a, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, since the oxide 230b is provided under the oxide 230c, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the region 234 provided in the oxide 230b is surrounded by the oxide 230a, the oxide 230c, the regions 232a, and 232b, and the concentration of impurities such as hydrogen and nitrogen in the region can be kept low. Can be kept high.
  • a semiconductor device using the oxide 230 having such a structure has favorable electrical characteristics and high reliability.
  • the oxide 230 has a curved surface between the side surface and the upper surface. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used as the metal oxide to be the region 234. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • the region 234 preferably has a stacked structure with oxides having different atomic ratios of metal atoms.
  • the metal oxide used for the oxide 230b has an atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. Is larger than the atomic ratio of the element M in the constituent elements.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230c a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • An oxide can be used.
  • the said composition shows the atomic ratio in the oxide formed on the board
  • Ga: Zn 1: 3: 4 as the oxide 230a
  • In: Ga: Zn 4: 2: 3 as the oxide 230b
  • In: Ga: Zn 1: 3: 4 as the oxide 230c.
  • the oxides 230a and 230c having a wide energy gap may be referred to as a wide gap
  • the oxide 230b having a relatively narrow energy gap may be referred to as a narrow gap.
  • the wide gap and the narrow gap will be described in [Configuration of metal oxide]. The above combination is preferable because the oxide 230b can be sandwiched between the oxide 230a and the oxide 230c having a higher gallium content.
  • the region 231 is a region where resistance is reduced by adding a metal atom such as indium or an impurity to the metal oxide provided as the oxide 230. Note that each region has higher conductivity than at least the oxide 230b in the region 234. Note that in order to add impurities to the region 231, for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, or an ion doping method in which an ionized source gas is added without mass separation A dopant that is at least one of a metal element such as indium and an impurity may be added using a plasma immersion ion implantation method or the like.
  • the insulator 274 including an element serving as an impurity can be formed in contact with the oxide 230, whereby the impurity can be added to the region 231.
  • the resistance of the region 231 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies.
  • elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 may include one or more of the above elements.
  • a film that extracts and absorbs oxygen contained in the region 231 may be used as the insulator 274.
  • oxygen vacancies are generated in the region 231.
  • hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancy, the resistance of the region 231 is reduced.
  • the region 232 is a region in which a metal atom selected from the above elements M such as gallium is added to the metal oxide provided as the oxide 230.
  • a metal atom selected from the above elements M such as gallium is added to the metal oxide provided as the oxide 230.
  • metal atoms for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, or ion doping in which an ionized source gas is added without mass separation.
  • a metal element such as gallium may be added using a plasma immersion ion implantation method or the like.
  • the region 232 the content of the element M such as gallium in the oxide 230 is higher than that in the region 234 or the region 231, so that the region 232 can be a region in which permeation of hydrogen or oxygen is suppressed.
  • the element M such as gallium can be added to the region 232 by forming a film containing the element M such as gallium in contact with the oxide 230 by a sputtering method, a CVD method, or an ALD method.
  • the resistance of the region 232 may be reduced.
  • the high-resistance region is not formed between the region 234 where the channel is formed and the region 232, the on-state current and mobility of the transistor can be increased.
  • the region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed.
  • leakage current at the time of non-conduction can be reduced.
  • the insulator 250 functions as a gate insulating film.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • the amount of desorbed oxygen converted to oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3.0 ⁇ 10 20.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
  • the insulator 250 By providing the insulator from which oxygen is released by heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b.
  • the region 232 is provided adjacent to the region 234, mixing of hydrogen from the region 231 into the region 234 and diffusion of oxygen supplied to the region 234 in the direction of the region 231 can be suppressed.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • the conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a.
  • As the conductor 260a titanium nitride or the like is preferably used.
  • As the conductor 260b a metal having high conductivity such as tungsten can be used.
  • the conductor 260 Overlap is preferably performed with an insulator such as the insulator 250 interposed therebetween and the oxide 230c. That is, it is preferable that the conductor 205, the insulator 220, the insulator 222, the insulator 224, the oxide 230c, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230.
  • the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .
  • An insulator 272 functioning as a barrier film is provided so as to be in contact with the side surface of the insulator 250 and cover the conductor 260.
  • the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulator including one or both of aluminum and hafnium can be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • oxygen in the insulator 250 can be prevented from diffusing outside.
  • entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed.
  • an upper surface and a side surface of the conductor 260 and a side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • the insulator 272 functions as a barrier for protecting the gate electrode and the gate insulating film.
  • the impurity element contained in the structure provided around the transistor 200 is diffused, so that the region 231a and the region 231b or the region There is a risk that 232a and the region 232b are electrically connected.
  • the insulator 272 by forming the insulator 272, impurities such as hydrogen and water can be prevented from entering the insulator 250 and the conductor 260, and oxygen in the insulator 250 can be reduced. Can be prevented from spreading outside. Therefore, when the first gate voltage is 0 V, the source region and the drain region can be prevented from being electrically connected directly or through the region 232 or the like.
  • the insulator 274 is provided to cover the insulator 272, the oxide 230, and the insulator 224.
  • the insulator 274 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • the insulator 274 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.
  • oxygen can be prevented from being transmitted through the insulator 274 and supplying oxygen to oxygen vacancies in the regions 231 a and 231 b, thereby reducing the carrier density.
  • impurities such as water or hydrogen which are transmitted through the insulator 274 and mixed into the region 234 can be suppressed.
  • the insulator 274 preferably includes at least one of hydrogen and nitrogen.
  • an impurity such as hydrogen or nitrogen can be added to the region 231 of the oxide 230, so that the resistance of the region 231 can be reduced.
  • An insulator 280 that functions as an interlayer film is preferably provided over the insulator 274.
  • the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the insulator 280 may have a stacked structure including similar insulators.
  • 2A, 2B, 2C, and 2D are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention.
  • a cell 600 illustrated in FIG. 2 includes the transistor 200 described above and the capacitor 100 in the same layer, so that part of the structure forming the transistor 200 is part of the structure forming the capacitor 100. And can be used together. That is, part of the structure of the transistor 200 may function as part of the structure of the capacitor 100.
  • the capacitor 200 when the capacitor 200 is partially or entirely overlapped with the transistor 200, the total area of the projected area of the transistor 200 and the projected area of the capacitor 100 can be reduced.
  • the transistor 200 is formed in the same process as the capacitor 100. Therefore, since the process can be shortened, productivity can be improved.
  • FIGS an example of the cell array of this embodiment is illustrated in FIGS.
  • a cell array can be formed by arranging the transistor 200 including the transistor 200 and the capacitor 100 illustrated in FIG. 2 in a matrix or matrix.
  • FIG. 3A is a circuit diagram illustrating an embodiment in which the cells 600 illustrated in FIG. 2 are arranged in a matrix.
  • a first gate of a transistor included in the cell 600 arranged in the row direction is electrically connected to a common WL (WL01, WL02, WL03).
  • one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06).
  • the transistor included in each cell 600 may be provided with the second gate BG.
  • the threshold value of the transistor can be controlled by the potential applied to BG.
  • the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor.
  • the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.
  • FIG. 3B shows a circuit 610 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. It is sectional drawing extracted. That is, FIG. 3B is a cross-sectional view of the cell 600a and the cell 600b.
  • the cell 600a includes a transistor 200a and a capacitor 100a.
  • the cell 600b includes a transistor 200b and a capacitor 100b.
  • FIG. 4A is a circuit diagram showing a mode different from FIG. 3A in a circuit in which the cells 600 shown in FIG. 2 are arranged in a matrix.
  • one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03).
  • the BL is also electrically connected to one of a source and a drain of a transistor included in a cell arranged in the column direction.
  • the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06).
  • the transistor included in each cell 600 may be provided with the second gate BG.
  • the threshold value of the transistor can be controlled by the potential applied to BG.
  • the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor.
  • the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.
  • FIG. 4B illustrates a circuit 620 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. 4A. It is sectional drawing extracted. That is, FIG. 4B is a cross-sectional view of the cell 600a and the cell 600b.
  • the cell 600a includes a transistor 200a and a capacitor 100a.
  • the cell 600b includes a transistor 200b and a capacitor 100b.
  • One of a source and a drain of the transistor 200a and one of a source and a drain of the transistor 200b are both electrically connected to BL02.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 functioning as an interlayer film.
  • a conductor 252 (a conductor 252a, a conductor 252b, a conductor 252c, and a conductor 252d) which is electrically connected to the transistor 200 and functions as a plug is provided.
  • the conductor 252 is formed in contact with the inner wall of the opening of the insulator 280.
  • the height of the upper surface of the conductor 252 and the height of the upper surface of the insulator 280 can be approximately the same.
  • the transistor 200 has a structure in which the conductor 252 has two layers, the present invention is not limited to this.
  • the conductor 252 may have a single layer or a stacked structure including three or more layers.
  • the capacitor 100 has a structure in common with the transistor 200.
  • the capacitor 100 in which part of the region 231 provided in the oxide 230 of the transistor 200 functions as one of the electrodes of the capacitor 100 is described.
  • the capacitor 100 includes a part of the region 231 of the oxide 230, the insulator 274, and the conductor 130 over the insulator 274. Furthermore, it is preferable that at least a part of the conductor 130 overlap with a part of the region 231.
  • Part of the region 231 of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 130 functions as the other of the electrodes of the capacitor 100. That is, the region 231 has a function as one of a source and a drain of the transistor 200 and a function as one of the electrodes of the capacitor 100. Part of the insulator 274 functions as a dielectric of the capacitor 100.
  • the conductor 130 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Although not shown, the conductor 130 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the insulator 280 is preferably provided so as to cover the insulator 274 and the conductor 130. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that the insulator 280 may have a stacked structure including similar insulators.
  • the insulator 280 preferably has a lower dielectric constant than the insulator 214.
  • parasitic capacitance generated between the wirings can be reduced.
  • the insulator 280 functioning as an interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3)
  • an insulator such as (Ba, Sr) TiO 3 (BST) can be used in a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the conductor 252a, the conductor 252b, the conductor 252c, and the conductor 252d are provided in the opening formed in the insulator 280 or the like. Note that the upper surfaces of the conductor 252a, the conductor 252b, the conductor 252c, and the conductor 252d may have substantially the same height as the upper surface of the insulator 280.
  • the conductor 252a is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274. Since the resistance of the region 231a is reduced, the contact resistance between the conductor 252a and the region 231a can be reduced.
  • the conductor 252b is in contact with the conductor 130 that is one of the electrodes of the capacitor 100 through an opening formed in the insulator 280.
  • the conductor 252c is in contact with the conductor 260 functioning as the first gate electrode of the transistor 200 through the insulator 280, the insulator 274, and the opening formed in the insulator 272.
  • the conductor 252d is formed of the conductor 205 functioning as the second gate electrode of the transistor 200 through an opening formed in the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator 220. Is in contact with.
  • the conductor 252a is preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230.
  • the conductor 252a is preferably in contact with both or one of the side surface on the C side and the side surface on the D side on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 252a may be in contact with the side surface on the A side at the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 252a is in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, so that the contact area of the conductor 252a and the oxide 230 is not increased without increasing the contact area.
  • the contact area between the conductor 252a and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • the conductor 252 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 252 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the insulator 274 and the conductor in contact with the insulator 280 have a function of suppressing transmission of impurities such as water or hydrogen, as in the conductor 205a.
  • impurities such as water or hydrogen
  • the conductor 205a is preferably used.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 280 can be prevented from entering the oxide 230 through the conductor 252.
  • an insulator having a function of suppressing transmission of impurities such as water or hydrogen may be provided in contact with the inner walls of the openings of the insulator 274 and the insulator 280 in which the conductor 252 is embedded.
  • an insulator that can be used for the insulator 214, for example, aluminum oxide is preferably used. Accordingly, impurities such as hydrogen and water from the insulator 280 and the like can be prevented from entering the oxide 230 through the conductor 252.
  • the insulator can be formed with good coverage by forming the insulator using, for example, an ALD method or a CVD method.
  • a conductor functioning as a wiring may be provided in contact with the upper surface of the conductor 252.
  • a conductive material containing tungsten, copper, or aluminum as a main component is preferably used.
  • a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate may be used as the substrate.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate may have elasticity.
  • the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate which is a flexible substrate for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used.
  • a substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • the substrate which is a flexible substrate for example, a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
  • Insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
  • a high-k material having a high relative dielectric constant is used for the insulator that functions as a gate insulator, so that transistors can be miniaturized and highly integrated. Become.
  • an insulator functioning as an interlayer film a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
  • Insulators having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium-containing oxides, aluminum and hafnium-containing oxynitrides, silicon and hafnium-containing oxides, silicon And oxynitride having hafnium or nitride having silicon and hafnium.
  • Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.
  • silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.
  • a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used as the insulator 222 and the insulator 214.
  • the insulator 222 and the insulator 214 can be formed using an insulator containing one or both of aluminum and hafnium.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • Examples of the insulator 220, the insulator 224, and the insulator 250 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum,
  • An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, silicon oxide, silicon oxynitride, or silicon nitride is preferably included.
  • the insulator 224 and the insulator 250 that function as gate insulators have a structure in which aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide is in contact with the oxide 230, so that silicon oxide or silicon oxynitride is included. It is possible to prevent silicon to be mixed into the oxide 230.
  • the insulator 224 and the insulator 250 by using silicon oxide or silicon oxynitride in contact with the oxide 230, aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide, and silicon oxide or silicon oxynitride In some cases, a trap center is formed at the interface. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.
  • the insulator 274 functioning as a dielectric includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, and hafnium nitride oxide
  • hafnium nitride, hafnium aluminate, or the like may be used.
  • a stacked structure of a high-k material such as aluminum oxide and a material with high dielectric strength such as silicon oxynitride is preferable.
  • the capacitive element 100 can secure a sufficient capacity with the high-k material, and the dielectric strength is improved with a material having a high dielectric strength. Therefore, electrostatic breakdown of the capacitive element 100 is suppressed, and the reliability of the capacitive element 100 is improved. Can be improved.
  • the insulator 216 and the insulator 280 preferably include an insulator with a low relative dielectric constant.
  • the insulator 216 and the insulator 280 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, It is preferable to have silicon oxide or resin having holes.
  • the insulator 216 and the insulator 280 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or empty It is preferable to have a laminated structure of silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.
  • the insulator 272 include aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, and silicon nitride oxide. Alternatively, silicon nitride or the like may be used.
  • Conductor a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc.
  • a material containing one or more elements can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed using the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260, the conductor 205, the conductor 130, and the conductor 252 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium,
  • a material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide semiconductor a metal oxide functioning as an oxide semiconductor
  • the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
  • the oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
  • the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • composition of metal oxide A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.
  • CAAC c-axis aligned crystal
  • CAC Cloud-aligned Composite
  • CAC-OS or CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is an electron serving as carriers. It is a function that does not flow.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily.
  • CAC-OS or CAC-metal oxide by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor).
  • OS amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in the distortion.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • the CAAC-OS is an oxide semiconductor with high crystallinity.
  • CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
  • the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and different properties.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • an oxide semiconductor with low carrier density is preferably used.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the oxide semiconductor has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less in SIMS. Preferably, it is 5 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • an oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIG. 6A is a cross-sectional view of the transistor 201 in the channel length direction.
  • FIG. 6B is a cross-sectional view of the transistor 202 in the channel length direction.
  • FIG. 6C is a cross-sectional view of the transistor 203 in the channel length direction.
  • a transistor 201 illustrated in FIG. 6A is different from the transistor 200 in at least the structure of the insulator over the conductor 260 and the shape of the insulator 272.
  • the insulator 270 is provided over the conductor 260, and the insulator 271 is provided over the insulator 270.
  • An insulator 272 is provided so as to be in contact with at least the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270.
  • the side surface of the oxide 230c and the side surface of the insulator 272 share the same surface.
  • the insulator 274 is provided so as to cover the insulator 224, the oxide 230, the insulator 272, the insulator 270, and the insulator 271.
  • the insulator 270 can function as a barrier film.
  • the insulator 270 can be formed using a material similar to that of the insulator 272, and an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used.
  • an insulator including one or both of aluminum and hafnium can be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Thereby, the oxidation of the upper part of the conductor 260 can be prevented.
  • impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
  • the insulator 271 can function as a hard mask when the conductor 260 is processed.
  • the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 ° to 100 °, preferably 80 ° to 95 °. It can be.
  • the insulator 272 to be formed next can be formed into a desired shape.
  • the insulator 272 is provided so as to be in contact with at least the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270.
  • the top surface and the side surface of the conductor 260 and the side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. .
  • the insulator 270 and the insulator 272 function as a top barrier and a side barrier that protect the gate electrode and the gate insulating film, respectively.
  • the oxide 230 includes the region 232, and similarly to the transistor 200, the entry of hydrogen from the region 231 to the region 234 and the diffusion of oxygen supplied to the region 234 toward the region 231 are suppressed. can do. Therefore, the transistor 201 has favorable electrical characteristics and improved reliability.
  • the transistor 202 illustrated in FIG. 6B is a transistor in that at least the shape of the oxide 230c and the insulator 272, the conductor 263 is provided over the oxide 230, and the insulator 274 is not provided. Different from 200.
  • the side surface of the oxide 230c and at least one side surface of the insulator 250 and the conductor 260 share the same surface.
  • a conductor 263 is provided over the region 231.
  • oxygen in the oxide 230 in contact with the conductor 263 is absorbed by the conductor 263, oxygen vacancies are generated in the oxide 230, and the metal element from the conductor 263
  • impurity elements such as hydrogen and nitrogen are mixed in the oxide 230 in contact with the conductor 263, so that the resistance of the region is reduced and the region 231 is formed.
  • the insulator 272 is provided so as to cover the insulator 224, the conductor 263, the oxide 230, the insulator 250, and the conductor 260.
  • the insulator 272 is provided so as to be in contact with at least the side surface of the insulator 250 and cover the conductor 260.
  • an upper surface and a side surface of the conductor 260 and a side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Accordingly, oxidation of the conductor 260 and mixing of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed. Therefore, the insulator 272 functions as a barrier that protects the gate electrode and the gate insulating film.
  • the oxide 230 includes the region 232, and similarly to the transistor 200, the entry of hydrogen from the region 231 to the region 234 and the diffusion of oxygen supplied to the region 234 toward the region 231 are suppressed. can do. Accordingly, the transistor 202 has favorable electrical characteristics and improved reliability.
  • a transistor 203 illustrated in FIG. 6C is different from the transistor 201 illustrated in FIG. 6A in at least the width of the region 232 in the oxide 230 and the gallium concentration in the region 231.
  • the width of the region 232 approximately matches the width of the insulator 272.
  • an element M such as gallium is added to the region 231.
  • the region 231 in contact with the insulator 274 has a low resistance as in the transistor 200.
  • the oxide 230 includes a region 232, and similarly to the transistor 200, the entry of hydrogen from the region 231 to the region 234 and the diffusion of oxygen supplied to the region 234 toward the region 231 are suppressed. can do. Therefore, the transistor 203 has favorable electrical characteristics and improved reliability.
  • FIGS. 7 to 21 a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. 7 to 21,
  • (B) of each figure is sectional drawing corresponding to the site
  • (C) of each figure is sectional drawing corresponding to the site
  • (D) of each figure is sectional drawing corresponding to the site
  • a substrate (not shown) is prepared, and an insulator 214 is formed over the substrate.
  • the insulator 214 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD (ALD) method. (Atomic Layer Deposition) method or the like can be used.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed.
  • the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • an aluminum oxide film is formed as the insulator 214 by a sputtering method.
  • the insulator 214 may have a multilayer structure.
  • an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method.
  • a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.
  • an insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 216 by a CVD method.
  • openings are formed in the insulator 216 and the insulator 214.
  • the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • the insulator 214 may be used as an etching stopper film when the insulator 216 is etched to form a groove.
  • a silicon oxide film is used for the insulator 216 that forms the groove
  • a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used as the insulator 214 as an insulating film that functions as an etching stopper film.
  • a conductive film to be the conductor 205a is formed.
  • the conductive film preferably includes a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductor to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
  • a metal nitride as the conductor 205a, it is possible to prevent the metal from diffusing out of the conductor 205a even when a metal that easily diffuses such as copper is used in the conductor 205b described later.
  • a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as tungsten or copper is formed as the conductive film to be the conductor 205b.
  • the conductive film to be the conductor 205a and part of the conductive film to be the conductor 205b are removed, and the insulator 216 is exposed.
  • the conductive film to be the conductor 205a and the conductive film to be the conductor 205b remain only in the opening. Accordingly, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 7). Note that part of the insulator 216 may be removed by the CMP treatment.
  • the insulator 220 is formed over the insulator 216 and the conductor 205.
  • the insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 is formed over the insulator 220.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator including one or both of aluminum and hafnium is preferably used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 222 is preferably formed by an ALD method.
  • the insulator 222 formed by the ALD method has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 7).
  • heat treatment is preferably performed.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.
  • the first heat treatment may be performed in a reduced pressure state.
  • heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be.
  • impurities such as hydrogen and water contained in the insulator 224 can be removed.
  • plasma treatment containing oxygen in a reduced pressure state may be performed as the heat treatment.
  • the plasma treatment including oxygen it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • a power source for applying RF (Radio Frequency) may be provided on the substrate side.
  • High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side.
  • plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.
  • the heat treatment can also be performed after the insulator 220 is formed and after the insulator 222 is formed. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.
  • treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed.
  • an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 7).
  • the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • the proportion of oxygen contained in the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.
  • the oxide film is formed by a sputtering method
  • the In-M-Zn oxide target can be used.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed.
  • the ratio of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed.
  • a transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed.
  • the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 8).
  • the insulator 224 may be processed into an island shape. Further, half etching may be performed on the insulator 224. By performing half etching on the insulator 224, the insulator 224 is formed in a state where the insulator 224 remains also under the oxide 230c formed in a later step. Note that the insulator 224 can be processed into an island shape when the insulating film 272A, which is a subsequent step, is processed. In that case, the insulator 222 may be used as an etching stopper film.
  • the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased.
  • the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.
  • a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, for example, at the ends of the oxide 230a and the oxide 230b.
  • membrane coverage in a subsequent film-forming process improves by not having a corner
  • the oxide film may be processed by a lithography method.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultra violet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do.
  • the etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after the oxide film is etched.
  • the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a, the oxide 230b, or the like.
  • impurities include fluorine and chlorine.
  • Cleaning is performed in order to remove the impurities and the like.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning using pure water or carbonated water may be performed.
  • ultrasonic cleaning using pure water or carbonated water is performed.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 9).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film 250A is exposed to the oxygen plasma, whereby oxygen is supplied to the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
  • the conductive film 260A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a transistor with a low driving voltage can be provided.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • an instantaneous heating method such as a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas, or an LRTA (Lamp Rapid Thermal Anneal) method using lamp light may be used.
  • the added dopant diffuses over the entire region 232 of the oxide 230, so that the affinity between the element M added as the dopant and the element included in the oxide 230 can be improved.
  • the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched to form the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 10).
  • the side surface of the insulator 250, the side surface of the conductor 260a, and the side surface of the side surface of the conductor 260b are preferably in the same plane.
  • the same surface shared by the side surface of the insulator 250, the side surface of the conductor 260a, and the side surface of the conductor 260b is preferably substantially perpendicular to the substrate. That is, in the cross-sectional shape, the insulator 250, the conductor 260a, and the conductor 260b are preferably as acute and large as possible with respect to the top surface of the oxide 230.
  • an angle formed by the side surfaces of the insulator 250, the conductor 260a, and the conductor 260b and the top surface of the oxide 230 may be an acute angle.
  • the angle formed by the side surfaces of the insulator 250, the conductor 260a, and the conductor 260b and the upper surface of the oxide 230 is preferably as large as possible.
  • the insulator 250 and the conductor 260 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
  • the etching may etch the upper portion of the region of the oxide film 230C that does not overlap with the insulator 250.
  • the thickness of the region of the oxide film 230C that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
  • a mask 262 is formed over the oxide film 230C (see FIG. 11).
  • the mask 262 may be any mask that can be removed in a later step, and a resist mask or a hard mask made of an insulator or a conductor can be used. At this time, the conductor 260 is preferably not covered with the mask 262.
  • a metal element is added using the mask 262 and the conductor 260 as a mask.
  • gallium is added to the oxide film 230C, the oxide 230b, and the oxide 230a by an ion implantation method, so that the region 232 is formed (see FIG. 12).
  • addition of a metal element may be performed by making the advancing direction of a dopant and the normal line direction of a board
  • part of the region 232 and part of the conductor 260 can be overlapped.
  • the metal element is added while the substrate is inclined.
  • an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the conductor 260, and the mask 262 (see FIG. 13).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage.
  • the insulating film 272 ⁇ / b> A having a uniform thickness can be formed on the side surfaces of the insulator 250 and the conductor 260 even in the step portion formed by the conductor 260 and the like.
  • the oxide film 230C, the insulator 250, and the conductor 260 are covered with the insulating film 272A in a region not covered with the mask 262. Therefore, the insulator 250 and the conductor 260 which overlap with the oxide 230a and the oxide 230b and the peripheral portion thereof are not covered with the mask 262 but are covered with the insulating film 272A.
  • the insulator 250 and the conductor 260 are preferably covered entirely with the insulating film 272A without being covered with the mask 262.
  • the insulating film 272A over the mask 262 is removed by a lift-off method, so that the insulator 272 that is in contact with the side surface of the insulator 250 and covers the conductor 260 is formed (see FIG. 14). ).
  • part of the oxide film 230C is removed by etching using the insulator 272 as a mask to form an oxide 230c (see FIG. 15). Note that in this step, the top surface and side surfaces of the oxide 230b and part of the side surfaces of the oxide 230a may be removed.
  • an insulator 274 containing a dopant is formed so as to cover the insulator 224, the oxide 230, and the insulator 272 so as to be in contact with the region 231 (see FIG. 16).
  • an insulator 274 containing hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, or the like as a dopant is formed so as to be in contact with the region 231 of the oxide 230.
  • the resistance of the region 231 is reduced by the formation of the insulator 274 and heat treatment after the formation.
  • the resistance of the oxide is reduced by the oxygen vacancies in the oxide 230 formed by the insulator 274 extracting oxygen in the oxide 230, the impurities added by diffusion into the dopant region 231 contained in the insulator 274, and the added impurities. This is considered to be caused by the formation of oxygen vacancies due to oxygen, the formation of carriers due to the bond between oxygen vacancies and impurities, or a combination thereof.
  • the resistance of the region 232 may be reduced also in the region 232 due to formation of oxygen vacancies or impurity diffusion.
  • the resistance of the oxide 230 may be reduced by adding a metal atom such as indium or a dopant such as an impurity.
  • a method for adding a dopant an ion implantation method in which ionized source gas is added by mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like is used. Can do. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
  • the dopant may be added by plasma treatment.
  • plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, or an ashing apparatus, and the dopant can be added to the oxides 230a, 230b, and 230c.
  • silicon nitride, silicon nitride oxide, or silicon oxynitride formed by a CVD method can be used as the insulator 274.
  • silicon nitride oxide is used as the insulator 274.
  • the region 231a and the region 231b can be formed in a film formation atmosphere of the insulator 274 such as hydrogen or nitrogen.
  • Impurity elements are added. Oxygen vacancies are formed by the added impurity element around the region in contact with the insulator 274 of the oxide 230, and the impurity element enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. At that time, the diffusion of impurities into the region 232 that is not in contact with the insulator 274 may reduce the resistance of the region 232.
  • the concentration of at least one of hydrogen and nitrogen be higher in the region 231a and the region 231b than in the region 234.
  • the concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • the concentration of hydrogen or nitrogen in the region 234 the distance from the vicinity of the center of the region overlapping the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the insulator 250 in the oxide 230b) is approximately. What is necessary is just to measure the density
  • the resistance of the region 231 is reduced by adding an element that forms oxygen vacancies or an element trapped by oxygen vacancies.
  • elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 may include one or more of the above elements.
  • the region 232 may also contain the above element. In this case, the resistance of the region 232 is also reduced.
  • a film that extracts and absorbs oxygen contained in the region 231 may be used as the insulator 274.
  • oxygen vacancies are generated in the region 231.
  • hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancy, the resistance of the region 231 is reduced.
  • oxygen contained in the region 232 may be extracted by the insulator 274, and the above-described element may be captured by oxygen vacancies generated thereby. In this case, the resistance of the region 232 is also reduced.
  • the insulator 274 is formed as an insulator including an element serving as an impurity or an insulator from which oxygen is extracted from the oxide 230
  • the insulator 274 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD. This can be done using methods.
  • the insulator 274 including the element serving as an impurity is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. By performing deposition in such an atmosphere, oxygen vacancies are formed around the oxide 230b and the oxide 250c that do not overlap with the insulator 250, and the oxygen vacancies are bonded to an impurity element such as nitrogen or hydrogen. Thus, the carrier density can be increased. In this manner, the region 231a and the region 231b with reduced resistance can be formed.
  • silicon nitride, silicon nitride oxide, or silicon oxynitride can be used by, for example, a CVD method. In this embodiment, silicon nitride oxide is used as the insulator 274.
  • the source region and the drain region can be formed in a self-aligned manner by forming the insulator 274. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.
  • an impurity element such as nitrogen or hydrogen can be prevented from being mixed into the conductor 260 and the insulator 250. it can.
  • an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260 and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
  • the region 231 is formed by reducing the resistance of the oxide 230 by forming the insulator 274; however, this embodiment is not limited thereto.
  • dopant addition treatment or plasma treatment may be used, or a plurality of these may be combined to form each region.
  • the oxide 230 may be subjected to plasma treatment using the insulator 272 as a mask.
  • the plasma treatment may be performed in an atmosphere containing an element that forms oxygen vacancies or an element trapped by oxygen vacancies.
  • plasma treatment may be performed using argon gas and nitrogen gas.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the added dopant diffuses to the entire region 231 of the oxide 230 and further to the region 232, so that the on-state current of the transistor 200 can be increased.
  • the insulator 280 is formed over the insulator 274 (see FIG. 17).
  • the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.
  • silicon oxynitride is used as the insulating film.
  • the insulator 280 is preferably formed so that an upper surface thereof has flatness.
  • the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280.
  • the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process.
  • the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process.
  • the top surface of the insulator 280 is not necessarily flat.
  • an opening reaching the region 231 of the oxide 230, the conductor 260, and the conductor 205 is formed in the insulator 280, the insulator 274, the insulator 272, the insulator 224, the insulator 222, and the insulator 220.
  • the opening may be formed using a lithography method.
  • the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 252a and the conductor 252b are provided in contact with the side surface of the oxide 230.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 252 having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIG. 18).
  • the conductor 252a is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274. Since the resistance of the region 231a is reduced, the contact resistance between the conductor 252a and the region 231a can be reduced.
  • the conductor 252b is in contact with the region 231b functioning as the other of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274.
  • the conductor 252c is in contact with the conductor 260 functioning as the first gate electrode of the transistor 200 through the insulator 280, the insulator 274, and the opening formed in the insulator 272.
  • the conductor 252d is formed of the conductor 205 functioning as the second gate electrode of the transistor 200 through an opening formed in the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator 220. Is in contact with.
  • the conductors 252a and 252b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surfaces of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with both or one of the side surface on the C side and the side surface on the D side (the side surface on the E side and the side surface on the F side) on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 252a and the conductor 252b may be in contact with the side surface on the A side and the side surface on the B side, respectively, on the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact portions of the conductor 252a and the conductor 252b and the oxide 230 are formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductors 252a and 252b and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 7 to 18, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • the area of the mask 262B shown in FIG. 19 increases from the side in contact with the oxide film 230C upward.
  • the opening provided in 262B has a so-called reverse taper shape that narrows upward from the side in contact with the oxide film 230C.
  • the resist has a laminated structure of two or more layers, and the lower resist is made of a material having higher sensitivity to light, electron beam, or the like than the upper resist, or at the time of development.
  • the material may be easily dissolved in the developer.
  • a metal element is added using the mask 262B and the conductor 260 as a mask to form regions 232 in the oxide film 230C, the oxide 230b, and the oxide 230a (FIG. 20). reference.).
  • the region 232 is formed along the opening provided in the mask 262B. That is, the region 232 is formed along the mask 262B having the largest area or along the narrowest opening. Therefore, even in a region where the mask 262B is not in contact with the oxide film 230C, when the mask 262B is provided above, the metal element is not added to the region.
  • addition of a metal element may be performed by making the advancing direction of a dopant and the normal line direction of a board
  • part of the region 232 and part of the conductor 260 can be overlapped.
  • the metal element is added while the substrate is inclined.
  • an insulating film is formed in a manner similar to the insulating film 272A illustrated in FIG. At this time, the insulating film is not formed in the mask 262B on the side surface that becomes an overhang or on the oxide film 230C covered with the mask 262B.
  • An insulator 272B is formed on the upper surface and part of the side surface of the mask 262B, and the insulator 272 is formed so as to cover the oxide film 230C, the insulator 250, and the conductor 260 that are not covered by the mask 262B ( (See FIG. 21.) That is, the insulator 272 and the insulator 272B are separated, and part of the mask 262B is not covered with the insulator.
  • the structure shown in FIG. 14 can be obtained by removing the mask 262B and removing the insulating film 272A over the mask 262B by a lift-off method. After that, the transistor 200 can be manufactured through a process similar to that described in ⁇ Method 1 for manufacturing a semiconductor device>.
  • FIGS. 22 to 32 a method for manufacturing a semiconductor device including the transistor 201 according to the present invention will be described with reference to FIGS. 22 to 32, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site
  • an oxide 230a and an oxide 230b are formed over the insulator 224 as illustrated in FIG.
  • the oxide film 230C, the insulating film 250A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b (FIG. 22).
  • the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B can be formed by the method described in ⁇ Method 1 for manufacturing semiconductor device>.
  • Heat treatment may be performed after the conductive film 260B is formed.
  • the heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed.
  • treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.
  • the insulating film 270A may be formed after the heat treatment.
  • the insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxidation of the conductor 260 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
  • the insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.
  • the insulator 271 functions as a hard mask.
  • the side surface of the insulator 250, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.
  • the insulating film 271A is etched to form the insulator 271. Subsequently, using the insulator 271 as a mask, the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form the insulator 250 and the conductor 260 (conductor 260a and conductor 260b), Then, an insulator 270 is formed (see FIG. 23). Even after the processing, a post-process may be performed without removing the hard mask. The hard mask can function as a hard mask even in the addition of a dopant performed in a later step.
  • a mask 262 is formed in a manner similar to FIG. 11 by the method described in ⁇ Method 1 for Manufacturing Semiconductor Device> (see FIG. 24).
  • a metal element is added using the mask 262, the insulator 271, the insulator 270, and the conductor 260 as a mask by the method described in ⁇ Method 1 for manufacturing a semiconductor device>, and the oxide film 230C
  • the region 232 is formed in the oxide 230b and the oxide 230a (see FIG. 25).
  • addition of a metal element may be performed by making the advancing direction of a dopant and the normal line direction of a board
  • part of the region 232 and part of the conductor 260 can be overlapped.
  • the metal element is added while the substrate is inclined.
  • the mask 262 is removed (see FIG. 26).
  • an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the conductor 260, the insulator 270, and the insulator 271 by a method described in ⁇ Semiconductor device manufacturing method 1> (FIG. 27). reference.).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage.
  • the insulating film 272 ⁇ / b> A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the step portion formed by the conductor 260 and the like. be able to.
  • anisotropic etching is performed on the insulating film 272A to form the insulator 272 in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270 (see FIG. 28).
  • anisotropic etching dry etching is preferably performed.
  • the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.
  • the insulator 270 can remain even if the insulating film 272A over the insulator 270 is removed. Further, the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is set higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C, thereby oxidizing the oxide. The insulating film 272A on the side surfaces of the oxide 230a and the oxide 230b through the film 230C can be removed.
  • part of the oxide film 230C is removed by etching using the insulator 250, the conductor 260, the insulator 270, the insulator 271 and the insulator 272 as a mask to form an oxide 230c (see FIG. 29). Note that in this step, the top surface and side surfaces of the oxide 230b and part of the side surfaces of the oxide 230a may be removed.
  • an insulator 274 containing a dopant is formed by a method described in ⁇ Method 1 for Manufacturing Semiconductor Device> as in FIG.
  • the insulator 274 is formed to cover the insulator 224, the oxide 230, the insulator 271, and the insulator 272 so as to be in contact with the region 231 (see FIG. 30).
  • the resistance of the region 231 is reduced by the formation of the insulator 274 and heat treatment after the formation.
  • the resistance of the region 231 may be reduced by adding a metal element such as indium and a dopant which is at least one of impurities.
  • a dopant addition method an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. Further, plasma treatment may be used.
  • Heat treatment may be performed after the insulator 274 is formed or after the dopant is added. By performing the heat treatment, the added dopant diffuses to the entire region 231 of the oxide 230 and further to the region 232, so that the on-state current of the transistor 200 can be increased.
  • an insulator 280 is formed over the insulator 274 by a method described in ⁇ Method 1 for Manufacturing Semiconductor Device> as in FIG. 17 (see FIG. 31).
  • the insulator 280, the insulator 274, the insulator 270, the insulator 271, the insulator 224, the insulator 222, and the insulator 220 reach the region 231 of the oxide 230, the conductor 260, and the conductor 205.
  • Form an opening may be formed using a lithography method.
  • the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 252a and the conductor 252b are provided in contact with the side surface of the oxide 230.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a part of the conductive film to be the conductor 252 is removed by CMP treatment, and the insulator 280 is exposed.
  • a conductive body 252 having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIG. 32).
  • the conductor 252a is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274. Since the resistance of the region 231a is reduced, the contact resistance between the conductor 252a and the region 231a can be reduced.
  • the conductor 252b is in contact with the region 231b functioning as the other of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274.
  • the conductor 252c is in contact with the conductor 260 functioning as the first gate electrode of the transistor 200 through the insulator 280, the insulator 274, the insulator 270, and the opening formed in the insulator 271. .
  • the conductor 252d is formed of the conductor 205 functioning as the second gate electrode of the transistor 200 through an opening formed in the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator 220. Is in contact with.
  • the conductors 252a and 252b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surfaces of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with both or one of the side surface on the C side and the side surface on the D side (the side surface on the E side and the side surface on the F side) on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 252a and the conductor 252b may be in contact with the side surface on the A side and the side surface on the B side, respectively, on the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact portions of the conductor 252a and the conductor 252b and the oxide 230 are formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductors 252a and 252b and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • a semiconductor device including the transistor 201 can be manufactured. As illustrated in FIGS. 22 to 32, the transistor 201 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • FIGS. 33 to 39 a method for manufacturing a semiconductor device including the transistor 202 according to the present invention will be described with reference to FIGS. Further, in FIGS. 33 to 39, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site
  • the oxide film 230 ⁇ / b> C, the insulating film 250 ⁇ / b> A, the conductive film 260 ⁇ / b> A, A conductive film 260B is sequentially formed. Subsequently, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched to form the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (FIG. 33.). This step is different from the step ⁇ Semiconductor device manufacturing method 1> in that the oxide film 230C is etched to form the oxide 230c.
  • the conductor 263 and the mask 264 are formed over the insulator 224 and the oxide 230b.
  • the conductor 263 also functions as a mask in the metal element addition step and as a conductor that is electrically connected to the region 231.
  • the conductor 263 is formed so as not to contact the conductor 260 (see FIG. 34).
  • the conductor 263 has a function of extracting oxygen from the region 231 of the oxide 230 during or after film formation to generate oxygen vacancies in the region 231 and a function of diffusing metal elements and impurities in the region 231. It is preferable to use a material having one or both. By using such a material, the resistance of the region 231 is reduced. Note that when the conductor 263 is formed by a sputtering method, impurities are mixed into the oxide 230 during film formation, or so-called mixing, so-called mixing of the metal element into the oxide 230 occurs, so that the region 231 has low resistance. Is preferable.
  • a resist mask can be used as the mask 264.
  • a conductor to be the conductor 263 is formed over the insulator 224, the oxide 230, the insulator 250, and the conductor 260, a mask 264 is formed over the conductor, and the conductor is processed by etching or the like.
  • the conductor 263 can be formed.
  • the conductor material used for the conductor 263 a material different from that of the conductor 260a and the conductor 260b is preferably used.
  • the conductor 263 is preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surface of the oxide 230.
  • the conductor 263 is preferably in contact with both or one of the side surface on the C side and the side surface on the D side (the side surface on the E side and the side surface on the F side) on the side surface that intersects the channel width direction of the oxide 230.
  • the conductor 263 may be in contact with the side surface on the A side and the side surface on the B side, respectively, on the side surface that intersects the channel length direction of the oxide 230.
  • the conductor 263 is in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, so that the contact area of the conductor 263 and the oxide 230 can be increased without increasing the upper area.
  • the contact area of the conductor can be increased, and the contact resistance between the conductor 263 and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • the metal element is added using the conductor 263, the mask 264, and the conductor 260 as a mask by the method described in ⁇ Method 1 for manufacturing a semiconductor device>, and the oxide 230b and the oxide A region 232 is formed in 230a (see FIG. 35).
  • addition of a metal element may be performed by making the advancing direction of a dopant and the normal line direction of a board
  • part of the region 232 and part of the conductor 260 can be overlapped.
  • the metal element is added while the substrate is inclined.
  • the metal element may be added after the mask 264 is removed first, or the mask 264 may be removed after the metal element is added. In the former case, the metal element is added using the conductor 263 and the conductor 260 as a mask.
  • the insulator 272 is formed so as to cover the insulator 224, the oxide 230, the conductor 263, the insulator 250, and the conductor 260 by a method described in ⁇ Method 1 for manufacturing a semiconductor device> (FIG. 37). reference.).
  • the insulator 272 is preferably formed by an ALD method with excellent coverage. By using the ALD method, even in a step portion formed by the conductor 260, the conductor 263, and the like, the thickness is uniform with respect to the side surfaces of the insulator 250, the conductor 260, the insulator 270, and the conductor 263. An insulator 272 having the above can be formed.
  • an insulator 280 is formed over the insulator 272 by a method described in ⁇ Method 1 for Manufacturing Semiconductor Device> as in FIG. 17 (see FIG. 38).
  • openings that reach the conductor 263, the conductor 260, and the conductor 205 are formed in the insulator 280, the insulator 272, the insulator 224, the insulator 222, and the insulator 220.
  • the opening may be formed using a lithography method.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 252 is removed by CMP treatment, and the insulator 280 is exposed. As a result, the conductive film 252 is formed only in the opening, whereby the conductor 252 having a flat upper surface can be formed (see FIG. 39).
  • the conductor 252a is in contact with the conductor 263 through an opening formed in the insulator 280 and the insulator 272, and is electrically connected to the region 231a functioning as one of the source region and the drain region of the transistor 200. To do. Since the resistance of the region 231a is reduced, the electrical resistance between the conductor 252a and the region 231a can be reduced.
  • the conductor 252b is in contact with the conductor 263 through an opening formed in the insulator 280 and the insulator 272, and is electrically connected to the region 231b functioning as the other of the source region and the drain region of the transistor 200. Connect to.
  • the conductor 252c is in contact with the conductor 260 functioning as the first gate electrode of the transistor 200 through the opening formed in the insulator 280 and the insulator 272.
  • the conductor 252d is formed of the conductor 205 functioning as the second gate electrode of the transistor 200 through an opening formed in the insulator 280, the insulator 272, the insulator 224, the insulator 222, and the insulator 220. Is in contact with.
  • a semiconductor device including the transistor 202 can be manufactured. As illustrated in FIGS. 33 to 39, the transistor 202 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • FIGS. 40 to 46 a method for manufacturing a semiconductor device including the transistor 203 according to the present invention will be described with reference to FIGS. 40 to 46, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site
  • the insulator 250, the conductor 260 (the conductor 260a and the conductor 260b), the insulator 270, and the insulator 271 are formed as described in ⁇ Semiconductor device manufacturing method 3>.
  • a metal element is added using the insulator 271, the insulator 270, and the conductor 260 as a mask by the method described in ⁇ Method 1 for manufacturing a semiconductor device>, and the oxide film 230C, the oxide 230b, and the oxide 230a are added.
  • a region 232 is formed in (see FIG. 40).
  • addition of a metal element may be performed by making the advancing direction of a dopant and the normal line direction of a board
  • part of the region 232 and part of the conductor 260 can be overlapped.
  • the metal element is added while the substrate is inclined.
  • an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the conductor 260, the insulator 270, and the insulator 271 by a method described in ⁇ Method 1 for manufacturing a semiconductor device> (FIG. 41). reference.).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage.
  • the insulating film 272 ⁇ / b> A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the step portion formed by the conductor 260 and the like. be able to.
  • anisotropic etching is performed on the insulating film 272A to form the insulator 272 in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270 (see FIG. 42).
  • anisotropic etching dry etching is preferably performed.
  • the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.
  • the insulator 270 can remain even if the insulating film 272A over the insulator 270 is removed. Further, the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is set higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C, thereby oxidizing the oxide. The insulating film 272A on the side surfaces of the oxide 230a and the oxide 230b through the film 230C can be removed.
  • part of the oxide film 230C is removed by etching using the insulator 250, the conductor 260, the insulator 270, the insulator 271 and the insulator 272 as a mask to form an oxide 230c (see FIG. 43). ). Note that in this step, the top surface and side surfaces of the oxide 230b and part of the side surfaces of the oxide 230a may be removed.
  • an insulator 274 containing a dopant is formed by a method described in ⁇ Method 1 for Manufacturing Semiconductor Device> as in FIG.
  • the insulator 274 is formed to cover the insulator 224, the oxide 230, the insulator 271, and the insulator 272 so as to be in contact with part of the region 232 of the oxide 230 (see FIG. 44).
  • the resistance of the oxide 230 in contact with the insulator 274 is reduced, and the region 231 is formed.
  • the region 232 covered with the insulator 272 is not in contact with the insulator 274, but oxygen in the region 232 is extracted by film formation of the insulator 274 or heat treatment after the film formation, and oxygen vacancies are generated. May occur or impurities such as hydrogen may diffuse to reduce resistance.
  • the resistance of the region 231 may be reduced by adding a metal element such as indium and a dopant that is at least one of impurities.
  • a dopant addition method an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. Further, plasma treatment may be used.
  • Heat treatment may be performed after the insulator 274 is formed or after the dopant is added. By performing the heat treatment, the added dopant diffuses to the entire region 231 of the oxide 230 and further to the region 232, so that the on-state current of the transistor 200 can be increased.
  • an insulator 280 is formed over the insulator 274 by a method shown in ⁇ Method 1 for Manufacturing Semiconductor Device> as in FIG. 17 (see FIG. 45).
  • the insulator 280, the insulator 274, the insulator 270, the insulator 271, the insulator 224, the insulator 222, and the insulator 220 reach the region 231 of the oxide 230, the conductor 260, and the conductor 205.
  • Form an opening may be formed using a lithography method.
  • the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 252a and the conductor 252b are provided in contact with the side surface of the oxide 230.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 252 having a flat upper surface can be formed by the conductive film remaining only in the opening (see FIG. 46).
  • the conductor 252a is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274. Since the resistance of the region 231a is reduced, the contact resistance between the conductor 252a and the region 231a can be reduced.
  • the conductor 252b is in contact with the region 231b functioning as the other of the source region and the drain region of the transistor 200 through the opening formed in the insulator 280 and the insulator 274.
  • the conductor 252c is in contact with the conductor 260 functioning as the first gate electrode of the transistor 200 through the insulator 280, the insulator 274, the insulator 270, and the opening formed in the insulator 271. .
  • the conductor 252d is formed of the conductor 205 functioning as the second gate electrode of the transistor 200 through an opening formed in the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator 220. Is in contact with.
  • the conductors 252a and 252b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surfaces of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with both or one of the side surface on the C side and the side surface on the D side (the side surface on the E side and the side surface on the F side) on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 252a and the conductor 252b may be in contact with the side surface on the A side and the side surface on the B side, respectively, on the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 252a and the conductor 252b are in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact portions of the conductor 252a and the conductor 252b and the oxide 230 are formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductors 252a and 252b and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • FIG. 47 is a diagram showing a case where a metal element is added to the oxide 230 to form the region 232, in which the traveling direction of the dopant is different from the normal direction of the substrate.
  • An oxide, a conductor, and an insulator included in the transistor 203 are provided over the base body 401.
  • the base body 401 includes the above-described substrate such as a substrate made of a semiconductor material such as silicon or an insulating substrate such as quartz or glass.
  • the base body 401 may include elements such as transistors and capacitors, and wirings.
  • a circuit may be constituted by the element and the wiring.
  • the substrate 401 is set on a stage 410 of an ion implantation apparatus, an ion doping apparatus, a plasma immersion ion implantation apparatus, or a plasma processing apparatus.
  • the stage 410 shown in FIGS. 47A and 47B has an electrostatic chuck mechanism, and is provided with an electrode 412 to which a positive potential is applied and an electrode 414 to which a negative potential is applied. ing.
  • the base body 401 is fixed to the stage 410 by applying a positive potential and a negative potential to the electrode 412 and the electrode 414, respectively.
  • the fixing of the base body 401 to the stage 410 is not limited to the electrostatic chuck.
  • the substrate 401 may be physically fixed to the stage 410, and a mechanical chuck or the like can be used.
  • the normal direction of the base body 401 is + ⁇ ( ⁇ is 1 ° or more and 60 ° or less, preferably 3 ° or more and 45 ° or less, more preferably 5 ° or more and 30 from the traveling direction of the dopant.
  • the stage 410 is tilted so as to tilt (below °), and a metal element is added (see FIG. 47A).
  • a region 232a is also formed in the oxide film 230C, the oxide 230b, and the oxide 230a that overlap with the conductor 260.
  • the conductor 260 as an axis, the conductor 260 or the like is used as a mask in part of the oxide film 230C, the oxide 230b, and the oxide 230a located opposite to the region 232a, and no metal element is added.
  • the normal direction of the base body 401 is ⁇ ( ⁇ is 1 ° or more and 60 ° or less, preferably 3 ° or more and 45 ° or less, more preferably 5 ° or more from the direction of travel of the dopant.
  • the stage 410 is tilted so as to tilt (30 ° or less), and a metal element is added (see FIG. 47B).
  • a region 232a is also formed in the oxide film 230C, the oxide 230b, and the oxide 230a that overlap with the conductor 260.
  • the oxide film 230C, the oxide 230b, and the oxide 230a overlapping with the conductor 260 are added.
  • the region 232a and the region 232b can be formed.
  • Such a metal element addition method is described in ⁇ Semiconductor Device Manufacturing Method 1>, ⁇ Semiconductor Device Manufacturing Method 2>, ⁇ Semiconductor Device Manufacturing Method 3>, and ⁇ Semiconductor Device Manufacturing Method 4>. Is also applicable.
  • the region 232 can be provided in part of the oxide 230 overlapping with the conductor 260.
  • the transistor 203 can be manufactured by forming the insulator 272, the oxide 230c, and the insulator 274 in accordance with the above manufacturing method.
  • a semiconductor device including the transistor 203 can be manufactured. As shown in FIGS. 40 to 47, the transistor 203 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device in which fluctuation in electrical characteristics is suppressed, stable electrical characteristics, and reliability is improved can be provided.
  • a semiconductor device capable of holding data for a long period can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a novel semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a highly productive semiconductor device can be provided.
  • a semiconductor device with a high degree of design freedom can be provided.
  • a semiconductor device that can reduce power consumption can be provided.
  • a semiconductor device in which a manufacturing process is simplified and a manufacturing method thereof can be provided. Further, according to one embodiment of the present invention, a semiconductor device with a reduced area and a manufacturing method thereof can be provided.
  • the memory device illustrated in FIG. 48 includes the transistor 200, the cell 600 including the capacitor 100, and the transistor 300.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the transistor 200 and the capacitor 100 have a common structure, the projected area is small, and miniaturization and high integration are possible.
  • the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300.
  • the wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 48 has characteristics that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing).
  • predetermined charge is given to the gate of the transistor 300 (writing).
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
  • the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V th_H when the gate of the transistor 300 is supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present.
  • the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”.
  • the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
  • the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V 0 (> V th_H ).
  • the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
  • the semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • transistor 300 illustrated in FIGS. 48A and 48B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
  • the insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • the insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
  • TDS temperature programmed desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is 10 ⁇ 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer.
  • a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324.
  • the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen.
  • tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 350 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are provided in this order.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
  • a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 370.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked.
  • a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
  • the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen.
  • An insulator 210 and an insulator 212 are sequentially stacked over the insulator 384. Any of the insulator 210 and the insulator 212 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
  • a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the cell 600 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the cell 600, characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the cell 600 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Accordingly, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the cell 600 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide included in the cell 600 can be suppressed. Therefore, it is suitable for use as a protective film for the cell 600.
  • the insulator 212 can be formed using the same material as the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like.
  • the conductor 218 functions as a plug or a wiring electrically connected to the cell 600 or the transistor 300.
  • the conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 200 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the cell 600 can be suppressed.
  • a cell 600 is provided above the insulator 212. Note that the structure of the cell 600 may be the cell 600 described in the above embodiment. Further, the cell 600 illustrated in FIG. 48 is an example, and the structure is not limited to the structure. An appropriate transistor may be used depending on a circuit configuration or a driving method.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • 2T type, 3T type a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied.
  • the OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 49 shows a configuration example of NOSRAM.
  • the NOSRAM 1600 illustrated in FIG. 49 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.
  • the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
  • the memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • one memory cell 1611 stores 3-bit (eight values) data.
  • the controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0].
  • the controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to be accessed.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • the column driver 1660 drives the source line SL and the bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
  • FIG. 50A is a circuit diagram illustrating a configuration example of the memory cell 1611.
  • the memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor.
  • the capacitive element C61 is a holding capacitor for holding the voltage of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • the bit line is a common bit line for writing and reading.
  • a writing bit line WBL and a reading bit line RBL may be provided. Good.
  • FIGS. 50C to 50E show other configuration examples of the memory cell.
  • FIGS. 50C to 50E show an example in which a write bit line and a read bit line are provided. However, as shown in FIG. May be provided.
  • a memory cell 1612 shown in FIG. 50C is a modification example of the memory cell 1611 and is obtained by changing a reading transistor to an n-channel transistor (MN61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • the OS transistor MO61 may be an OS transistor without a back gate.
  • a memory cell 1613 illustrated in FIG. 50D is a 3T-type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • a memory cell 1614 shown in FIG. 50E is a modified example of the memory cell 1613, in which the reading transistor and the selection transistor are changed to n-channel transistors (MN62 and MN63).
  • the transistors MN62 and MN63 may be OS transistors or Si transistors.
  • the OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.
  • the NOSRAM 1600 Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
  • the transistor 200 is used as the OS transistors MO61 and MO62
  • the capacitor 100 is used as the capacitors C61 and C62
  • the transistors MP61 and MN62 are used.
  • the transistor 300 can be used. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS.
  • DOSRAM registered trademark
  • amic Oxide Semiconductor RAM refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells.
  • OS memory is applied to DOSRAM as well as NOSRAM.
  • FIG. 51 shows a configuration example of the DOSRAM.
  • the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
  • MC-SA array 1420 a sense amplifier array 1420
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • Global bit lines GBLL and GBLR are stacked on the memory cell array 1422.
  • a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
  • the memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> -1425 ⁇ N-1>.
  • FIG. 52A shows a configuration example of the local memory cell array 1425.
  • the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 52B shows a circuit configuration example of the memory cell 1445.
  • the memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2.
  • the transistor MW1 has a function of controlling charging / discharging of the capacitor CS1.
  • the gate of the transistor MW1 is electrically connected to the word line WL, the first terminal is electrically connected to the bit line (BLL or BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1.
  • BLL or BLR bit line
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant voltage (for example, a low power supply voltage) is input to the terminal B2.
  • the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1.
  • the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated.
  • the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • the transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage at the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B1 may be changed according to the operation of the DOSRAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, the first terminal, or the second terminal of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.
  • the sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> -1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to the sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference.
  • the switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
  • bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier.
  • a global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form one bit line pair.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
  • the controller 1405 has a function of controlling the overall operation of the DOSRAM 1400.
  • the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of decoding an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
  • a column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column.
  • the switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413.
  • the plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
  • the column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • the global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference.
  • Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.
  • Data is written to the global bit line pair by the input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
  • One row of the local memory cell array 1425 is designated by the address signal.
  • the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line.
  • the local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data.
  • the switch array 1444 writes the data in the column specified by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair.
  • the global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
  • the DOSRAM 1400 Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
  • the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.
  • the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.
  • an FPGA field programmable gate array
  • OS-FPGA field programmable gate array
  • FIG. 53A shows a configuration example of the OS-FPGA.
  • the OS-FPGA 3110 shown in FIG. 53A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE.
  • the OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
  • the programmable area 3115 includes two input / output blocks (IOB) 3117 and a core (Core) 3119.
  • the IOB 3117 has a plurality of programmable input / output circuits.
  • the core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130.
  • the LAB 3120 includes a plurality of PLE 3121s.
  • FIG. 53B shows an example in which the LAB 3120 is composed of five PLE 3121s.
  • the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array.
  • the LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
  • the SB 3131 will be described with reference to FIGS. 54 (A) to 54 (C).
  • Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship.
  • the number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal.
  • the signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
  • the SB 3131 includes PRSs (programmable routing switches) 3133 [0] and 3133 [1].
  • the PRSs 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
  • FIG. 54B illustrates a circuit configuration example of the PRS 3133 [0].
  • PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration.
  • PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal.
  • the signals context [0] and word [0] are input to the PRS 3133 [0]
  • the signals context [1] and word [1] are input to the PRS 3133 [1].
  • the PRS 3133 [0] becomes active.
  • the PRS 3133 [0] includes a CM 3135 and a Si transistor M31.
  • the Si transistor M31 is a pass transistor controlled by the CM 3135.
  • the CM 3135 includes memory circuits 3137 and 3137B.
  • the memory circuits 3137 and 3137B have the same circuit configuration.
  • the memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32.
  • the memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.
  • the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitor 100 can be used as the capacitors C31 and CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.
  • the gate of the Si transistor M31 is the node N31
  • the gate of the OS transistor MO32 is the node N32
  • the gate of the OS transistor MOB32 is the node NB32.
  • Nodes N32 and NB32 are charge holding nodes of the CM 3135.
  • the OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0].
  • the OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.
  • the logic of data held in the memory circuits 3137 and 3137B has a complementary relationship. Therefore, either one of the OS transistors MO32 or MOB32 becomes conductive.
  • the PRS 3133 [0] While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
  • the PRS 3133 [0] is active.
  • the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
  • the OS transistor MO32 of the memory circuit 3137 is a source follower, so that the gate voltage of the Si transistor M31 increases due to boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
  • the CM 3135 also has a multiplexer function.
  • FIG. 55 shows a configuration example of the PLE 3121.
  • the PLE 3121 includes an LUT (Look Up Table) block (LUT block) 3123, a register block 3124, a selector 3125, and a CM 3126.
  • the LUT block 3123 is configured to select and output data according to inputs inA, inB, inC, and inD.
  • the selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
  • the PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
  • the register block 3124 is configured by a nonvolatile register.
  • the nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.
  • the register block 3124 includes OS-FFs 3140 [1] and 3140 [2]. Signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2].
  • the clock signal CLK1 is input to the OS-FF 3140 [1]
  • the clock signal CLK2 is input to the OS-FF 3140 [2].
  • FIG. 56A shows a configuration example of the OS-FF 3140.
  • the OS-FF 3140 includes an FF 3141 and a shadow register 3142.
  • the FF 3141 includes nodes CK, R, D, Q, and QB.
  • a clock signal is input to the node CK.
  • a signal user_res is input to the node R.
  • the signal user_res is a reset signal.
  • Node D is a data input node
  • node Q is a data output node.
  • Nodes Q and QB have a complementary logic relationship.
  • the shadow register 3142 functions as a backup circuit for the FF 3141.
  • the shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
  • the shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B.
  • the memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133.
  • the memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36.
  • the memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36.
  • Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, respectively, and are charge holding nodes.
  • Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.
  • the transistor 200 can be used as the OS transistors MO35 and MOB35, and the capacitor 100 can be used as the capacitors C36 and CB36. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.
  • the shadow register 3142 backs up the data in the FF 3141.
  • the node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 holds the backed up data even when the power is turned off.
  • the power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
  • the power consumption of the OS-FPGA 3110 can be effectively reduced.
  • An error that may occur in the memory circuit is a soft error due to the incidence of radiation.
  • a soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair.
  • An OS memory using an OS transistor has high soft error resistance. Therefore, by installing the OS memory, a highly reliable OS-FPGA 3110 can be provided.
  • FIG. 57 is a block diagram illustrating a configuration example of the AI system 4041.
  • the AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.
  • the arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014.
  • DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.
  • the control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access MemoryPROM 40 Memory, Memory Memory 4024).
  • the input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.
  • the arithmetic unit 4010 can execute learning or inference using a neural network.
  • the analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
  • the analog arithmetic circuit 4011 is preferably formed using an OS transistor.
  • An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021.
  • the DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • the input data may exceed 1000.
  • the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions.
  • the DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.
  • a NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.
  • the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit.
  • analog data refers to data having a resolution of 3 bits (8 values) or more. The multi-value data described above may be included in the analog data.
  • Data and parameters used for calculation of the neural network can be temporarily stored in the NOSRAM 4013.
  • the data and parameters may be stored in the memory provided outside the AI system 4041 via the CPU 4021.
  • the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.
  • the FPGA 4014 is an FPGA using an OS transistor.
  • the AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM).
  • a neural network connection such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can reduce the area of the memory compared to the FPGA configured with the SRAM. Therefore, even if a context switching function is added, the area increase is small.
  • the OS-FPGA can transmit data and parameters at high speed by boosting.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.
  • the AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed.
  • the PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.
  • the AI system 4041 preferably includes a GPU 4022.
  • the AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog calculation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.
  • the PLL 4023 has a function of generating a clock.
  • the AI system 4041 operates based on the clock generated by the PLL 4023.
  • the PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.
  • the AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM.
  • the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.
  • Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.
  • the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
  • the AI system 4041 includes an audio codec 4032 and a video codec 4033.
  • the audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).
  • the AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.
  • the analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory.
  • the flash memory has a limited number of rewritable times.
  • it is very difficult to form a multi-level flash memory in an embedded manner an arithmetic circuit and a memory are formed on the same die.
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy.
  • circuit design for separating data writing and reading becomes complicated.
  • the analog arithmetic circuit 4011 may use MRAM as an analog memory.
  • MRAM has a low resistance change rate and has a problem in terms of storage accuracy.
  • the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.
  • FIG. 58A shows an AI system 4041A in which the AI systems 4041 described in FIG. 57 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.
  • An AI system 4041A illustrated in FIG. 58A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number).
  • the AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.
  • FIG. 58B shows an AI system 4041B in which the AI system 4041 described in FIG. 57 is arranged in parallel as in FIG. 58A, and signals can be transmitted and received between systems via a network. is there.
  • An AI system 4041B illustrated in FIG. 58B includes a plurality of AI systems 4041_1 to 4041_n.
  • the AI systems 4041_1 to 4041_n are connected to each other via a network 4099.
  • the network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
  • the communication module can communicate via an antenna.
  • the Internet Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (Campure Area Network, MAN (MetropoliAwareNetwork), MAN (MetropoliAureNetwork), which are the foundations of the World Wide Web (WWW).
  • Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication.
  • LTE Long Term Evolution
  • GSM Global System for Mobile Communication: registered trademark
  • EDGE Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Emulsion
  • Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.
  • analog signals obtained by an external sensor or the like can be processed by separate AI systems.
  • information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information
  • various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor
  • analog signals can be processed by separate AI systems. it can.
  • signal processing or learning in each separate AI system the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.
  • the AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.
  • FIG. 59 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 shown in FIG. 59 includes a lead 7001 and a circuit portion 7003.
  • the AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004).
  • the circuit portion 7003 is provided with the various circuits described in the above embodiment in one die.
  • the circuit portion 7003 has a stacked structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.
  • QFP Quad Flat Package
  • a digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and OS memories such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.
  • FIG. 60 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
  • FIG. 60A shows a monitor 830.
  • the monitor 830 includes a display portion 831, a housing 832, a speaker 833, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
  • the monitor 830 can be operated with a remote controller 834.
  • the monitor 830 can function as a television device by receiving broadcast radio waves.
  • Broadcast radio waves that can be received by the monitor 830 include terrestrial waves or radio waves transmitted from satellites.
  • broadcast radio waves there are analog broadcasts, digital broadcasts, etc., and video and audio, or audio-only broadcasts.
  • broadcast radio waves transmitted in a specific frequency band in the UHF band (300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received.
  • the transfer rate can be increased and more information can be obtained.
  • an image having a resolution exceeding full high-definition can be displayed on the display unit 831. For example, an image having a resolution of 4K-2K, 8K-4K, 16K-8K, or higher can be displayed.
  • the monitor 830 may not have a tuner.
  • the monitor 830 can be connected to a computer and used as a computer monitor.
  • a monitor 830 connected to a computer can be viewed by a plurality of people at the same time, and can be used for a conference system. Further, the monitor 830 can be used in a video conference system by displaying computer information via the network or connecting the monitor 830 itself to the network.
  • the monitor 830 can also be used as digital signage.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • image processing such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing is performed. Can do. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • HDR high dynamic range
  • a video camera 2940 illustrated in FIG. 60B includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like.
  • the operation switch 2944 and the lens 2945 are provided on the housing 2941
  • the display portion 2944 is provided on the housing 2942.
  • the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941.
  • the housing 2941 and the housing 2942 are connected to each other by a connection portion 2946.
  • the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946.
  • the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • an AI system including the semiconductor device of one embodiment of the present invention for the image processing portion of the video camera 2940, shooting according to the environment around the video camera 2940 can be realized. Specifically, shooting can be performed with an optimal exposure according to the ambient brightness. In addition, when shooting under different lighting conditions, such as shooting in backlight or indoor and outdoor, high dynamic range (HDR) shooting can be performed.
  • HDR high dynamic range
  • the AI system can learn a photographer's habit and can assist in photographing. Specifically, by learning the camera shake of the photographer and correcting the camera shake during shooting, it is possible to minimize the image disturbance caused by the camera shake. Further, when using the zoom function during shooting, the direction of the lens and the like can be controlled so that the subject is always shot at the center of the image.
  • An information terminal 2910 illustrated in FIG. 60C includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
  • the display portion 2912 includes a display panel using a flexible substrate and a touch screen.
  • the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
  • the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold the control information of the above-described information terminal 2910, the control program, and the like for a long period.
  • image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed.
  • image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed.
  • inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased.
  • a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • the AI system can learn the user's habit and assist the operation of the information terminal 2910.
  • An information terminal 2910 equipped with an AI system can predict a touch input from the movement of a user's finger, the line of sight, and the like.
  • a laptop personal computer 2920 illustrated in FIG. 60D includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
  • the laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the laptop personal computer 2920 for a long period.
  • images such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing can be used. Processing can be performed. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • HDR high dynamic range
  • the AI system can learn a user's habit and assist the operation of the laptop personal computer 2920.
  • a laptop personal computer 2920 equipped with an AI system can predict a touch input to the display unit 2922 from the movement of a user's finger, a line of sight, or the like.
  • input prediction is performed based on past text input information and figures such as preceding and following texts and photographs, and conversion is assisted. Thereby, input mistakes and conversion mistakes can be reduced as much as possible.
  • FIG. 60E is an external view illustrating an example of an automobile
  • FIG. 60F illustrates a navigation device 860.
  • the automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.
  • the automobile 2980 includes an antenna, a battery, and the like.
  • the navigation device 860 includes a display unit 861, operation buttons 862, and an external input terminal 863.
  • the automobile 2980 and the navigation device 860 may be independent of each other, but it is preferable that the navigation device 860 is incorporated in the automobile 2980 and functions in conjunction with the automobile 2980.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the automobile 2980 and the navigation device 860 for a long period.
  • the AI system learns driving skills and habits of the driver, assists in safe driving, and uses gasoline or batteries. It is possible to assist driving that efficiently uses such fuel. Assisting safe driving not only learns the driver's driving skills and habits, but also learns driving behavior such as the speed and movement method of the car 2980, road information stored in the navigation device 860, etc.
  • the navigation device 860 can transmit the road information to the automobile 2980 to control the speed of the automobile 2980 and assist the steering operation.

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Abstract

L'invention concerne un dispositif à semi-conducteur ayant de bonnes propriétés électriques. Ce dispositif à semi-conducteur comprend un oxyde, un isolant et un conducteur chevauchant une première région de l'oxyde avec l'isolant interposé entre eux, l'oxyde contenant de l'In, un élément M (M est Al, Ga, Y ou Sn), et du Zn, et a une deuxième région adjacente à la première région et une concentration plus élevée de l'élément M dans la deuxième région que dans la première région.
PCT/IB2018/051210 2017-03-10 2018-02-27 Dispositif à semi-conducteur et procédé de fabrication d'un dispositif à semi-conducteur WO2018163012A1 (fr)

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