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WO2018163013A1 - Dispositif à semiconducteur et procédé de fabrication d'un dispositif à semiconducteur - Google Patents

Dispositif à semiconducteur et procédé de fabrication d'un dispositif à semiconducteur Download PDF

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Publication number
WO2018163013A1
WO2018163013A1 PCT/IB2018/051212 IB2018051212W WO2018163013A1 WO 2018163013 A1 WO2018163013 A1 WO 2018163013A1 IB 2018051212 W IB2018051212 W IB 2018051212W WO 2018163013 A1 WO2018163013 A1 WO 2018163013A1
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Prior art keywords
insulator
oxide
transistor
conductor
region
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PCT/IB2018/051212
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English (en)
Japanese (ja)
Inventor
山崎舜平
遠藤太一
奥野直樹
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株式会社半導体エネルギー研究所
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Publication of WO2018163013A1 publication Critical patent/WO2018163013A1/fr

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • the CPU has a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer, and forms an assembly of semiconductor elements on which electrodes serving as connection terminals are formed.
  • a semiconductor circuit such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components.
  • a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
  • the transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device).
  • IC integrated circuit
  • image display device also simply referred to as a display device.
  • a silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
  • a transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state.
  • a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
  • Patent Document 2 a technique of stacking oxide semiconductor layers having different electron affinities (or conduction band bottom levels) is disclosed (see Patent Document 2 and Patent Document 3).
  • An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor including a channel formation region, and a gate insulator, and the gate insulator is in contact with the channel formation region.
  • a second layer on the first layer, the second layer is a metal oxide, and the metal oxide has a root mean square roughness (RMS) of 1 ⁇ m ⁇ 1 ⁇ m. In this case, it is 0.4 nm or less.
  • RMS root mean square roughness
  • One embodiment of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor including a channel formation region, and a gate insulator, and the gate insulator is in contact with the channel formation region. And a second layer on the first layer, and the second layer is a metal oxide, and a ring-shaped pattern is observed in electron diffraction using an electron microscope for the metal oxide.
  • the metal oxide is hafnium aluminate or hafnium oxide.
  • hafnium oxide is deposited by sputtering at a deposition temperature of 130 ° C. or lower in a mixed atmosphere containing oxygen.
  • the first layer is silicon oxide, and the amount of desorbed oxygen molecules is 1.0 ⁇ 10 19 atoms / cm 3 or more in the TDS analysis.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a highly productive semiconductor device can be provided.
  • a semiconductor device capable of holding data for a long period can be provided.
  • a semiconductor device with high data writing speed can be provided.
  • a semiconductor device with a high degree of design freedom can be provided.
  • a semiconductor device that can reduce power consumption can be provided.
  • a novel semiconductor device can be provided.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device.
  • 1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • the figure explaining the cross section of the sample which concerns on an Example The figure explaining the cross-sectional TEM image of the sample which concerns on an Example.
  • the figure explaining the cross section of the sample which concerns on an Example The figure explaining the result of the TDS measurement of the sample which concerns on an Example.
  • a top view also referred to as a “plan view”
  • a perspective view a perspective view, and the like
  • some components may not be described in order to facilitate understanding of the invention.
  • description of some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region.
  • a current can flow. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.
  • the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or in a region where a channel is formed This is the length of the part.
  • the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor).
  • channel width Sometimes referred to as “channel width”).
  • the effective channel width may be larger than the apparent channel width, and the influence may not be negligible.
  • the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
  • the apparent channel width may be referred to as “surrounded channel width (SCW)”.
  • SCW surrounded channel width
  • channel width in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease.
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by mixing impurities.
  • impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • a silicon oxynitride film has a higher oxygen content than nitrogen in its composition.
  • oxygen is 55 atomic% to 65 atomic%
  • nitrogen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • the silicon nitride oxide film has a nitrogen content higher than that of oxygen.
  • nitrogen is 55 atomic% to 65 atomic%
  • oxygen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • the terms “film” and “layer” can be interchanged with each other.
  • the term “conductive layer” may be changed to the term “conductive film”.
  • the term “insulating film” may be changed to the term “insulating layer” in some cases.
  • the term “insulator” can be restated as an insulating film or an insulating layer.
  • the term “conductor” can be restated as a conductive film or a conductive layer.
  • the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
  • the transistors described in this specification and the like are field-effect transistors unless otherwise specified.
  • the transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of describing as an OS FET, it can be referred to as a transistor including an oxide or an oxide semiconductor.
  • ⁇ Configuration example of semiconductor device> 1A, 1B, and 1C are a top view and a cross-sectional view of the transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.
  • FIG. 1A is a top view of a semiconductor device including a transistor 200.
  • FIG. 1B and 1C are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A and also a cross-sectional view in the channel length direction of the transistor 200.
  • FIG. 1C is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 200.
  • some elements are omitted for clarity.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200, the insulator 210 functioning as an interlayer film, the insulator 212, and the insulator 280.
  • a conductor 203 (a conductor 203a and a conductor 203b) which is electrically connected to the transistor 200 and functions as a wiring
  • a conductor 240 (a conductor 240a and a conductor 240b) which functions as a plug are included. .
  • the conductor 203 is formed with a conductor 203a in contact with the inner wall of the opening of the insulator 212, and further has a conductor 203b formed inside.
  • the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be approximately the same.
  • the transistor 200 has a structure in which the conductor 203a and the conductor 203b are stacked, the present invention is not limited to this. For example, only the conductor 203b may be provided.
  • the conductor 240 is formed in contact with the inner wall of the opening of the insulator 280.
  • the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 280 can be approximately the same.
  • the transistor 200 has a structure in which the conductor 240 is a single layer, the present invention is not limited to this.
  • the conductor 240 may have a stacked structure of two or more layers.
  • the transistor 200 includes an insulator 214 and an insulator 216 which are disposed over a substrate (not shown), and a conductor 205 which is disposed so as to be embedded in the insulator 214 and the insulator 216.
  • the transistor 200 has a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this.
  • a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of three or more layers may be provided.
  • the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this.
  • FIG. 2 is an enlarged view of a region 239 in the vicinity of the channel surrounded by a broken line in FIG.
  • the oxide 230 includes a region 232 between a region 234 functioning as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) functioning as a source region or a drain region. (Region 232a and region 232b).
  • the region 231 functioning as a source region or a drain region is a region with high carrier density and low resistance.
  • the region 234 functioning as a channel formation region is a region having a lower carrier density than the region 231 functioning as a source region or a drain region.
  • the region 232 has a lower carrier density than the region 231 that functions as a source region or a drain region and a higher carrier density than the region 234 that functions as a channel formation region.
  • the region 232 functions as a junction region between the channel formation region and the source region or the drain region.
  • the region 232 may function as a so-called overlap region (also referred to as a Lov region) which overlaps with the conductor 260 functioning as a gate electrode.
  • a high resistance region is not formed between the region 231 functioning as a source region or a drain region and the region 234 functioning as a channel formation region, so that the on-state current of the transistor can be increased.
  • the oxide 230 is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • a transistor including an oxide semiconductor its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.
  • oxygen vacancies formed in the region 234 where the channel is formed in the oxide 230 can be reduced by supplying oxygen.
  • the insulator 250 containing oxygen may be provided in contact with the oxide 230.
  • the insulator 250 preferably contains more oxygen (hereinafter also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. When excess oxygen diffuses from the insulator 250 into the oxide 230, oxygen vacancies in the oxide 230 can be reduced.
  • the insulator 250 is preferably formed using an oxide material that has an excess oxygen region and from which part of oxygen is released by heating.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen molecule is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably in TDS (Thermal Desorption Spectroscopy) analysis, preferably
  • the oxide film has a thickness of 1.0 ⁇ 10 19 atoms / cm 3 or more, preferably 2.0 ⁇ 10 19 atoms / cm 3 , and more preferably 3.0 ⁇ 10 20 atoms / cm 3 .
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
  • silicon oxide having excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 252 preferably suppresses oxygen diffusion in order to efficiently supply excess oxygen included in the insulator 250 to the oxide 230.
  • the insulator 252 that suppresses diffusion of oxygen diffusion of excess oxygen into the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 due to excess oxygen can be suppressed.
  • the insulator 250 and the insulator 252 may function as part of the gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the insulator 252 is preferably formed using a metal oxide that is a high-k material with a high relative dielectric constant. With such a laminated structure, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the equivalent oxide thickness (EOT: equivalent oxide thickness) of the gate insulator while maintaining the physical thickness.
  • EOT equivalent oxide thickness
  • the on-state current can be improved without weakening the influence of the electric field from the conductor 260.
  • leakage current can be suppressed by maintaining the distance between the conductor 260 and the oxide 230 depending on the physical thickness of the insulator 250 and the insulator 252.
  • the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily increased. Can be adjusted appropriately.
  • a film with low crystallinity (or few crystals) or a film including an amorphous structure may be used as the insulator 252 as the insulator 252.
  • An oxide film with low crystallinity or an amorphous structure can diffuse oxygen contained in the oxide film to an adjacent insulator by heating.
  • excess oxygen is added from the insulator 252 to the insulator 250 due to a thermal history in a later process, and the insulator 250 is excessive.
  • An oxygen region can be easily formed.
  • a film with low crystallinity or a film including an amorphous structure has high flatness, and the interface between the insulator 250 and the insulator 252 can be in a favorable state.
  • the insulator 252 is a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium. Can be used.
  • hafnium oxide an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium.
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process.
  • an insulation whose root mean square roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 ⁇ m ⁇ 1 ⁇ m. Use your body.
  • RMS root mean square roughness
  • an insulator in which a circular (ring-shaped) pattern is observed in electron beam diffraction using an electron microscope may be used.
  • the insulator 272 is preferably provided in contact with the insulator 250 and the insulator 252.
  • the insulator 272 preferably has a function of suppressing diffusion of oxygen (eg, oxygen atoms and oxygen molecules). Since the insulator 272 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region included in the insulator 250 is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.
  • oxygen eg, oxygen atoms and oxygen molecules
  • a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided.
  • the conductor 203 is extended in the channel width direction and functions as a wiring for applying a potential to the conductor 205.
  • the conductor 203 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.
  • the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided in contact with the upper surface of the conductor 203.
  • the conductor 260 may function as a first gate (also referred to as a top gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked.
  • the threshold voltage of the transistor 200 can be made higher than 0 V and the off-state current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260 is 0 V can be reduced.
  • the conductor 205 By providing the conductor 205 over the conductor 203, the distance between the conductor 203 having the function of the first gate electrode and the wiring and the conductor 203 can be appropriately designed.
  • the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260 By providing the insulator 214, the insulator 216, and the like between the conductor 203 and the conductor 260, the parasitic capacitance between the conductor 203 and the conductor 260 can be reduced and the withstand voltage can be increased.
  • the switching speed of the transistor can be improved and a transistor having high frequency characteristics can be obtained. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulator 214 and the insulator 216. Note that the extending direction of the conductor 203 is not limited thereto, and the conductor 203 may be extended in the channel length direction of the transistor 200, for example.
  • the conductor 205 is provided so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG.
  • the conductor 205 is preferably provided larger than the region 234 in the oxide 230.
  • the conductor 205 is preferably extended also in a region outside the end portion in the channel width direction (W length direction) of the region 234 of the oxide 230b. . That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator outside the side surface in the channel width direction of the oxide 230b.
  • the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.
  • a transistor structure that electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the conductor 205 is in contact with the inner walls of the openings of the insulator 214 and the insulator 216, the conductor 205a is formed, and the conductor 205b is further formed inside.
  • the heights of the upper surfaces of the conductors 205a and 205b and the height of the upper surface of the insulator 216 can be approximately the same.
  • the transistor 200 has a structure in which the conductors 205a and 205b are stacked, the present invention is not limited to this. For example, only the conductor 205b may be provided.
  • the conductor 205a and the conductor 203a diffuse impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 ), a copper atom, and the like. It is preferable to use a conductive material having a function of suppressing (the above-described impurities are hardly transmitted). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the above-mentioned oxygen hardly transmits). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.
  • the conductivity can be prevented from being reduced due to oxidation of the conductor 205b and the conductor 203b.
  • a conductive material having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, the conductive material may be used as a single layer or a stacked layer as the conductor 205a and the conductor 203a. Accordingly, diffusion of impurities such as hydrogen and water to the transistor 200 side through the conductor 203 and the conductor 205 can be suppressed.
  • the conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above-described conductive material.
  • the conductor 203b functions as a wiring, a conductor having higher conductivity than the conductor 205b is preferably used.
  • a conductor having higher conductivity than the conductor 205b is preferably used.
  • a conductive material mainly containing copper or aluminum can be used.
  • the conductor 203b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the conductor 203b it is preferable to use copper for the conductor 203b. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, the characteristics of the transistor 200 may be deteriorated by diffusing into the oxide 230.
  • the insulator 214 can be made of copper diffusion by using a material such as aluminum oxide or hafnium oxide having low copper permeability.
  • the insulator 210 and the insulator 214 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor from the substrate side. Accordingly, the insulator 210 and the insulator 214 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, and the like) and copper atoms. It is preferable to use an insulating material having a function to prevent the above impurities from being transmitted. Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the above-mentioned oxygen is difficult to transmit).
  • oxygen for example, oxygen atoms and oxygen molecules
  • the insulator 210 aluminum oxide or the like is preferably used as the insulator 210, and silicon nitride or the like is preferably used as the insulator 214. Accordingly, diffusion of impurities such as hydrogen and water to the transistor side through the insulator 210 and the insulator 214 can be suppressed. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing to the substrate side through the insulator 210 and the insulator 214.
  • the insulator 214 can be provided over the conductor 203 by stacking the conductor 205 over the conductor 203.
  • the metal can be prevented from diffusing into a layer above the insulator 214.
  • the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214.
  • parasitic capacitance generated between the wirings can be reduced.
  • An insulator such as strontium (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) can be used as a single layer or a stacked layer.
  • strontium (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST) can be used as a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220, the insulator 222, and the insulator 224 function as gate insulators.
  • an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used as the insulator 224 in contact with the oxide 230. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the oxide film has a thickness of 0.0 ⁇ 10 19 atoms / cm 3 or more, more preferably 2.0 ⁇ 10 19 atoms / cm 3 , or 3.0 ⁇ 10 20 atoms / cm 3 or more.
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
  • the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side.
  • the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.
  • the insulator 222 is so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. As transistor miniaturization and higher integration progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, the physical film thickness can be maintained and the voltage can be reduced.
  • an insulator including one or both oxides of aluminum and hafnium which is an insulating material having a function of suppressing diffusion of impurities and oxygen (impermeability of impurities and oxygen) is preferably used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining 222 with a high-k insulator.
  • the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230b By including the oxide 230b over the oxide 230a, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230b is provided under the oxide 230c, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the oxide 230 preferably has a stacked structure with oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent element is larger than the atomic ratio of the element M in the constituent element in the metal oxide used for the oxide 230b. It is preferable. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is preferably higher than the energy at the lower end of the conduction band in a region where the energy at the lower end of the conduction band of the oxide 230b is low.
  • the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity in the region where the energy at the lower end of the conduction band of the oxide 230b is low.
  • the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined.
  • the defect state density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c is preferably low.
  • the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) in addition to oxygen, so that a mixed layer with a low density of defect states is formed.
  • the oxide 230b is an In—Ga—Zn oxide
  • an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.
  • the main path of carriers is a narrow gap portion formed in the oxide 230b. Since the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced, the influence on the carrier conduction due to interface scattering is small, and a high on-current is obtained. can get.
  • the oxide 230 preferably includes a region 231, a region 232, and a region 234. Note that at least part of the region 231 is in contact with the insulator 274 and preferably has at least one concentration of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.
  • the region 232 preferably has at least one concentration of a metal element such as indium, hydrogen, and nitrogen higher than the region 234 and lower than the region 231.
  • the region 231 and the region 232 are regions obtained by adding metal atoms such as indium and gallium or impurities to the metal oxide provided as the oxide 230.
  • the region 231 has higher conductivity than the region 234.
  • impurities for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, and an ionized source gas are added without mass separation.
  • a dopant which is at least one of a metal element such as indium and an impurity may be added using an ion doping method, a plasma immersion ion implantation method, or the like.
  • the insulator 274 including an element serving as an impurity is formed in contact with the oxide 230, whereby the impurity can be added to the region 231 and the region 232.
  • the region 231 by increasing the content of metal atoms such as indium in the oxide 230, electron mobility can be increased and resistance can be reduced.
  • the resistance of the region 231 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies.
  • elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 may include one or more of the above elements.
  • the region 234, the region 231, and the region 232 are formed in the oxide 230b; however, the region is not limited thereto, and for example, these regions include the oxide 230a and the oxide 230b.
  • the object 230c may also be formed.
  • the boundary of each region is displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this.
  • the region 232 may protrude to the conductor 260 side in the vicinity of the surface of the oxide 230b and recede to the conductor 240a side or the conductor 240b side in the vicinity of the lower surface of the oxide 230a.
  • the transistor 200 when the resistance of the region 232 is reduced, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; , And mobility can be increased.
  • the region 232 since the region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed.
  • leakage current at the time of non-conduction can be reduced.
  • gallium or the like when gallium or the like is added to the region 232, lateral diffusion of impurities such as hydrogen from the region 231 to the region 234 can be suppressed, and unintended reduction of the effective channel length can be suppressed.
  • the region 231a or the region 231b functions as a source region or a drain region.
  • at least part of the region 234 functions as a region where a channel is formed.
  • a curved surface is provided between the side surface of the oxide 230 and the upper surface of the oxide 230. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used as the metal oxide to be the region 234. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, or cerium. It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • the insulator 250 functions as a gate insulating film.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • the amount of desorbed oxygen converted to oxygen molecules is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1.0 ⁇ 10 19.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or more and 700 ° C. or less.
  • silicon oxide having excess oxygen silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and voids Silicon oxide can be used.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • the insulator 252 preferably suppresses oxygen diffusion in order to efficiently supply excess oxygen included in the insulator 250 to the oxide 230.
  • the insulator 252 that suppresses diffusion of oxygen diffusion of excess oxygen into the conductor 260 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed.
  • oxidation of the conductor 260 due to excess oxygen can be suppressed.
  • the insulator 250 and the insulator 252 may function as part of the gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the insulator 252 is preferably formed using a metal oxide that is a high-k material with a high relative dielectric constant. With such a laminated structure, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness.
  • EOT equivalent oxide thickness
  • the on-state current can be improved without weakening the influence of the electric field from the conductor 260.
  • leakage current can be suppressed by maintaining the distance between the conductor 260 and the oxide 230 depending on the physical thickness of the insulator 250 and the insulator 252.
  • the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily increased. Can be adjusted appropriately.
  • a film with low crystallinity (or few crystals) or a film including an amorphous structure may be used as the insulator 252 as the insulator 252.
  • An oxide film with low crystallinity or an amorphous structure can diffuse oxygen contained in the oxide film to an adjacent insulator by heating.
  • excess oxygen is added from the insulator 252 to the insulator 250 due to a thermal history in a later process, and the insulator 250 is excessive.
  • An oxygen region can be easily formed.
  • a film with low crystallinity or a film including an amorphous structure has high flatness, and the interface between the insulator 250 and the insulator 252 can be in a favorable state.
  • the insulator 252 is a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium. Can be used.
  • hafnium oxide an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium.
  • hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in a heat history in a later process.
  • an insulation whose root mean square roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 ⁇ m ⁇ 1 ⁇ m. Use your body.
  • RMS root mean square roughness
  • an insulator in which a circular (ring-shaped) pattern is observed in electron beam diffraction using an electron microscope may be used.
  • the conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. Similar to the conductor 205a, the conductor 260a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. It is preferable to use a conductive material having a suppressing function. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, oxygen atoms and oxygen molecules).
  • the conductor 260a has a function of suppressing oxygen diffusion
  • excess conductivity of the insulator 250 and the insulator 252 can prevent the conductor 260b from being oxidized and lowering in conductivity.
  • a conductive material having a function of suppressing oxygen diffusion for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductor 260 functions as a wiring, a conductor having high conductivity is preferably used.
  • a conductor having high conductivity is preferably used for the conductor 260b.
  • the conductor 260b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • a conductive oxide can be used as the conductor 260a.
  • a metal oxide that can be used as the oxide 230 is preferably used.
  • oxygen can be added to the insulator 250 and the insulator 252 so that oxygen can be supplied to the region 234 of the oxide 230. It becomes. Accordingly, oxygen vacancies in the region 234 of the oxide 230 can be reduced.
  • the conductor 260a When the above conductive oxide is used as the conductor 260a, it is preferable to use a conductor that can improve the conductivity of the conductor 260a by adding an impurity such as nitrogen to the conductor 260a.
  • a conductor that can improve the conductivity of the conductor 260a by adding an impurity such as nitrogen to the conductor 260a.
  • titanium nitride or the like is preferably used for the conductor 260b.
  • the conductor 260b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereover.
  • the conductor 260 when the conductor 205 extends to a region outside the end portion in the channel width direction of the oxide 230b, the conductor 260 is insulated in the region. It is preferable to overlap the body 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a stacked structure outside the side surface of the oxide 230b.
  • the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. .
  • an insulator 271 functioning as a barrier film or a hard mask 270 may be provided over the conductor 260b.
  • the side surface of the conductor 260 is substantially perpendicular to the substrate surface, specifically, the angle formed between the side surface of the conductor 260 and the substrate surface is 75 degrees.
  • the angle can be not less than 100 degrees and preferably not less than 80 degrees and not more than 95 degrees.
  • the insulator 272 functioning as a barrier film is provided in contact with the side surfaces of the insulator 250, the insulator 252, the conductor 260, and the insulator 270.
  • the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen For example, aluminum oxide or hafnium oxide is preferably used.
  • the oxygen in the insulator 250 and the insulator 252 can be prevented from diffusing to the outside.
  • entry of impurities such as hydrogen and water into the oxide 230 from the end portions of the insulator 250 and the insulator 252 and the like can be suppressed. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.
  • an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen covers the side surface of the conductor 260, the side surface of the insulator 250, and the side surface of the insulator 252. Can do. Accordingly, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260, the insulator 250, and the insulator 252. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.
  • a transistor when a transistor is miniaturized and a channel length is formed to be about 10 nm to 30 nm, an impurity element contained in a structure provided around the transistor 200 is diffused, so that a region 231a and a region 231b are formed. There is a risk of electrical conduction.
  • the first gate voltage when the first gate voltage is 0 V, the source region and the drain region can be prevented from being electrically connected.
  • the insulator 274 is provided so as to cover the insulator 271, the insulator 272, the oxide 230, and the insulator 224.
  • the insulator 274 is provided in contact with the top surfaces of the insulator 271 and the insulator 272 and in contact with a side surface of the insulator 272.
  • the insulator 274 an insulating material having a function of suppressing permeation of oxygen is preferably used.
  • the insulator 274 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.
  • the insulator 274 preferably includes at least one of hydrogen and nitrogen.
  • an impurity such as hydrogen or nitrogen is added to the oxide 230, so that the region 231 and the region 232 are formed in the oxide 230. Can do.
  • An insulator 280 that functions as an interlayer film is preferably provided over the insulator 274.
  • the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator similar to the insulator 210 may be provided over the insulator 280.
  • the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 280 and the insulator 274.
  • the conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween.
  • the heights of the upper surfaces of the conductors 240a and 240b may be approximately the same as the height of the upper surface of the insulator 280.
  • the conductor 240a is in contact with the region 231a that functions as one of the source region and the drain region of the transistor 200
  • the conductor 240b is in contact with the region 231b that functions as the other of the source region and the drain region of the transistor 200. Therefore, the conductor 240a can function as one of the source electrode and the drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode. Since the region 231a and the region 231b have low resistance, the contact resistance between the conductor 240a and the region 231a and the contact resistance between the conductor 240b and the region 231b can be reduced and the on-state current of the transistor 200 can be increased.
  • a conductor 240a is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 274.
  • a region 231a of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a.
  • a conductor 240b is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 274.
  • a region 231b of the oxide 230 is located at least at a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.
  • the conductor 240 a and the conductor 240 b are preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230.
  • the conductor 240a and the conductor 240b are preferably in contact with both or one of the side surface on the A3 side and the side surface on the A4 side on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 240a and the conductor 240b may be in contact with the side surface on the A1 side (A2 side) on the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 240a and the conductor 240b are in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the conductor 240a and the contact portion between the conductor 240b and the oxide 230 are formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductor 240a and the conductor 240b and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • the conductor 240a and the conductor 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductors 240a and 240b may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the insulator 274 and the conductor in contact with the insulator 280 have a function of suppressing transmission of impurities such as water or hydrogen, as in the conductor 205a.
  • impurities such as water or hydrogen
  • the conductor 205a is preferably used.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used.
  • the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from an upper layer than the insulator 280 can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b.
  • a conductor that functions by being in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b may be disposed.
  • a conductive material containing tungsten, copper, or aluminum as a main component is preferably used.
  • the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material. Note that like the conductor 203 and the like, the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate may be used as the substrate.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate may have elasticity.
  • the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate which is a flexible substrate for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used.
  • a substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • the substrate which is a flexible substrate for example, a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
  • Insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
  • the transistor when the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator.
  • a high-k material for the insulator functioning as a gate insulator, the physical film thickness can be maintained and the voltage can be reduced.
  • a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
  • Insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, silicon and hafnium. There are oxynitrides having silicon and nitrides having silicon and hafnium.
  • Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.
  • silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.
  • a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • the insulator 224 and the insulator 250 that function as part of the gate insulator are preferably insulators having an excess oxygen region.
  • insulators having an excess oxygen region For example, by using a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.
  • an insulator including one or more oxides of aluminum, hafnium, and gallium can be used.
  • a film with low crystallinity (or few crystals) or a film including an amorphous structure may be used as the insulator 222 and the insulator 252 .
  • An oxide film with low crystallinity or an amorphous structure can diffuse oxygen contained in the oxide film to an adjacent insulator by heating.
  • the insulator 224 and the insulator 224 are changed from the insulator 222 and the insulator 252 due to heat history in a later process. Excess oxygen is added to 250, and an excess oxygen region can be easily formed in the insulator 224 and the insulator 250.
  • a film having low crystallinity or a film including an amorphous structure has high flatness, and has an interface between the insulator 250 and the insulator 252, an interface between the insulator 220 and the insulator 222, and an insulator 222 and the insulator 224.
  • the interface with can be in a good state.
  • an insulation whose root mean square roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 ⁇ m ⁇ 1 ⁇ m. Use your body.
  • RMS root mean square roughness
  • an insulator in which a circular (ring-shaped) pattern is observed in electron beam diffraction using an electron microscope may be used.
  • the insulator 222 is preferably formed using silicon oxide or silicon oxynitride which is stable against heat.
  • the gate insulator has a heat-stable film and a laminated structure with a high relative dielectric constant, so that the equivalent oxide thickness (EOT) of the gate insulator can be reduced while maintaining the physical film thickness. It becomes.
  • the on-state current can be improved without weakening the influence of the electric field from the gate electrode. Further, leakage current can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed depending on the physical thickness of the gate insulator.
  • the insulator 212, the insulator 216, the insulator 271 and the insulator 280 preferably include an insulator having a low relative dielectric constant.
  • the insulator 212, the insulator 216, the insulator 271, and the insulator 280 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and It is preferable to include silicon oxide to which nitrogen is added, silicon oxide having holes, or a resin.
  • the insulator 212, the insulator 216, the insulator 271, and the insulator 280 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and the like. It is preferable to have a stacked structure of silicon oxide to which nitrogen is added or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen can be used.
  • the insulator 270 and the insulator 272 include aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, and silicon nitride oxide. Alternatively, silicon nitride or the like may be used.
  • Conductor a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc.
  • a material containing one or more elements can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed using the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260, the conductor 203, the conductor 205, and the conductor 240 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium
  • a material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium, and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide semiconductor a metal oxide functioning as an oxide semiconductor
  • the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
  • the oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
  • the oxide semiconductor is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • composition of metal oxide A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.
  • CAAC c-axis aligned crystal
  • CAC Cloud-aligned Composite
  • CAC-OS or CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is an electron serving as carriers. It is a function that does not flow.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily.
  • CAC-OS or CAC-metal oxide by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor).
  • OS amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in the distortion.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • the CAAC-OS is an oxide semiconductor with high crystallinity.
  • CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
  • the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and different properties.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • an oxide semiconductor with low carrier density is preferably used.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the oxide semiconductor has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • nitrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ 10 18. atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • an oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIGS. 3 to 11 (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site
  • a substrate (not shown) is prepared, and an insulator 210 is formed over the substrate.
  • the insulator 210 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD (ALD) method. (Atomic Layer Deposition) method or the like can be used.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed.
  • the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • an aluminum oxide film is formed as the insulator 210 by a sputtering method.
  • the insulator 210 may have a multilayer structure.
  • an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method.
  • a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.
  • the insulator 212 is formed over the insulator 210.
  • the insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 212 by a CVD method.
  • openings are formed in the insulator 212 and the insulator 210.
  • the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • the insulator 210 is preferably selected from an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove.
  • the insulator 210 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film as an insulating film functioning as an etching stopper film.
  • a conductive film to be the conductor 203a is formed.
  • the conductive film preferably includes a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductor to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 203a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
  • a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out of the conductor 203a even when a metal that easily diffuses such as copper is used in the conductor 203b described later.
  • a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203b.
  • the conductive film to be the conductor 203a and part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed.
  • the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening.
  • the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 3).
  • part of the insulator 212 may be removed by the CMP treatment.
  • the insulator 214 is formed over the insulator 212 and the conductor 203.
  • the insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that does not easily transmit copper, such as silicon nitride, as the insulator 214, even if a metal that easily diffuses such as copper is used for the conductor 203b, the metal is a layer above the insulator 214. Can be prevented from diffusing.
  • an insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 216 by a CVD method.
  • an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216.
  • Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • the conductive film to be the conductor 205a desirably includes a conductive material having a function of suppressing permeation of oxygen.
  • a conductive material having a function of suppressing permeation of oxygen for example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • tantalum nitride is formed by a sputtering method as the conductive film to be the conductor 205a.
  • a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed by a CVD method as the conductive film to be the conductor 205b, and tungsten is formed by a CVD method on the titanium nitride.
  • the conductive film to be the conductor 205a and part of the conductive film to be the conductor 205b are removed, and the insulator 216 is exposed.
  • the conductive films to be the conductors 205a and 205b remain only in the openings. Accordingly, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 3). Note that part of the insulator 212 may be removed by the CMP treatment.
  • the insulator 220 is formed over the insulator 216 and the conductor 205.
  • the insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 212 by a CVD method.
  • the insulator 222 is formed over the insulator 220.
  • an insulator containing one or both of aluminum and hafnium may be formed.
  • the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 is a film having low crystallinity (or few crystals) or a film including an amorphous structure.
  • An oxide film with low crystallinity or an amorphous structure can diffuse oxygen contained in the oxide film to an adjacent insulator by heating.
  • excess oxygen is added from the insulator 222 to the insulator 224 due to a thermal history in a later process, and an excess oxygen region is added to the insulator 224.
  • a film having low crystallinity or a film including an amorphous structure has high flatness, and can have a favorable interface with another film to be stacked.
  • An oxide film with low crystallinity or an amorphous structure that can be used for the insulator 222 has a deposition temperature of R.D. T.A. (RT: Room temperature. Note that in this specification, RT is a temperature at which heating is not performed intentionally) 200 ° C. or lower and a sputtering method in a mixed atmosphere containing oxygen. Can be membrane.
  • the film forming temperature is preferably 130 ° C. or lower, more preferably R.P. T.A. It is good to do.
  • a mixed atmosphere containing oxygen a mixed gas of oxygen and a rare gas or a mixed gas of oxygen and nitrogen can be used.
  • the root mean square roughness (RMS) measured using an atomic force microscope by sputtering under a mixed atmosphere containing a film forming temperature of 200 ° C. or less and oxygen is 0.
  • An insulator 222 having a thickness of 4 nm or less, preferably 0.3 nm or less, can be formed.
  • the insulator 222 in which a circular (ring-shaped) pattern is observed in electron beam diffraction using an electron microscope can be formed.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3).
  • silicon oxide is formed as the insulator 224 by a CVD method.
  • heat treatment is preferably performed.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. .
  • treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed.
  • the heat treatment can also be performed at the timing after the insulator 220 is formed and after the insulator 222 is formed. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.
  • plasma treatment including oxygen may be performed in a reduced pressure state.
  • an apparatus having a power source that generates high-density plasma using microwaves for example.
  • a power source for applying RF (Radio Frequency) may be provided on the substrate side.
  • High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side.
  • plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.
  • an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 4).
  • the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • the proportion of oxygen contained in the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.
  • the oxide film is formed by a sputtering method
  • the In-M-Zn oxide target can be used.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, more preferably 100%.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed.
  • a transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed.
  • the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
  • the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 5).
  • the insulator 224 may be processed into an island shape.
  • the insulator 222 can be used as an etching stopper film.
  • the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the upper surface of the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased.
  • the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.
  • a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230a. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
  • the oxide film may be processed by a lithography method.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do.
  • the etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after the oxide film is etched.
  • the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a, the oxide 230b, or the like.
  • impurities include fluorine and chlorine.
  • Cleaning is performed in order to remove the impurities and the like.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning using pure water or carbonated water may be performed.
  • ultrasonic cleaning using pure water or carbonated water is performed.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • the oxide film 230C, the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b. Film (see FIG. 6).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
  • an insulating film 250A is formed.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxynitride is preferably formed by a CVD method as the insulating film 250A.
  • the deposition temperature at the time of forming the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., particularly preferably around 400 ° C.
  • oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film 250A is exposed to the oxygen plasma, so that oxygen is supplied to the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
  • an insulating film 252A is formed over the insulating film 250A.
  • an insulator containing one or both of aluminum and hafnium may be formed.
  • the insulator including one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • An insulator including one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 252A has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 do not diffuse into the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
  • the insulating film 252A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 252A is a film having low crystallinity (or few crystals) or a film including an amorphous structure.
  • An oxide film with low crystallinity or an amorphous structure can diffuse oxygen contained in the oxide film to an adjacent insulator by heating.
  • excess oxygen is added from the insulating film 252A to the insulating film 250A due to a thermal history in a later process, and an excess oxygen region is added to the insulating film 250A.
  • a film having low crystallinity or a film including an amorphous structure has high flatness, and can have a favorable interface with another film to be stacked.
  • An oxide film with low crystallinity or an amorphous structure that can be used for the insulating film 252A has a deposition temperature of R.P.
  • a film can be formed by a sputtering method in a mixed atmosphere containing T and 200 ° C. and oxygen.
  • the film forming temperature is preferably 130 ° C. or lower, more preferably R.P. T (RT is a temperature that is not intentionally heated).
  • a mixed atmosphere containing oxygen a mixed gas of oxygen and a rare gas or a mixed gas of oxygen and nitrogen can be used.
  • the root mean square roughness (RMS) measured using an atomic force microscope by sputtering under a mixed atmosphere containing a film forming temperature of 200 ° C. or less and oxygen is 0.
  • An insulator 252A with a thickness of 4 nm or less, preferably 0.3 nm or less, can be formed.
  • an insulating film 252A in which a circular (ring-shaped) pattern is observed in electron beam diffraction using an electron microscope can be formed.
  • oxygen can be added to the insulating film 250A and an excess oxygen region can be formed in the insulating film 250A. .
  • oxygen vacancies can be compensated.
  • the insulating film 252A is formed by a sputtering method
  • ions and sputtered particles exist between the target and the substrate.
  • the target is connected to a power source and is supplied with the potential E0.
  • the substrate is given a potential E1 such as a ground potential.
  • the substrate may be electrically floating.
  • the magnitude relationship between the potentials is E2> E1> E0.
  • Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles are ejected from the target.
  • the sputtered particles adhere to and deposit on the film formation surface to form a film.
  • some ions recoil by the target pass through a film formed as recoil ions, and may be taken into the insulating film 250A and the insulator 224 in contact with the deposition surface.
  • ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some ions reach the inside of the insulating film 250 ⁇ / b> A and the insulator 224.
  • An excess oxygen region can be formed by introducing excess oxygen into the insulating film 250A and the insulator 224. Excess oxygen in the insulating film 250A and the insulator 224 is supplied to the oxide 230, so that oxygen vacancies in the oxide 230 can be filled.
  • oxygen can be introduced into the insulating film 250A and the insulator 224 while the insulating film 252A is formed.
  • excess oxygen introduced into the insulator 250 can be effectively contained.
  • a conductive film 260A and a conductive film 260B are formed.
  • the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed by a CVD method as the conductive film 260A
  • tungsten is formed by a CVD method as the conductive film 260B.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed.
  • excess oxygen is added from the insulator 252A to the insulator 250A and the insulator 224, so that an excess oxygen region can be easily formed in the insulator 250A and the insulator 224.
  • the insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, oxidation of the conductor 260 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250. In this embodiment, aluminum oxide is formed as the insulating film 270A by an ALD method.
  • the insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.
  • silicon oxide is formed by a CVD method as the insulating film 271A.
  • the insulating film 271A is etched to form the insulator 271.
  • the insulator 271 functions as a hard mask.
  • the side surface of the insulator 250, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.
  • the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form an oxide 230 (oxide 230a, oxide 230b, and oxide 230c).
  • 250, the insulator 252, the conductor 260 (the conductor 260a and the conductor 260b), and the insulator 270 are formed (see FIG. 7).
  • the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, the insulator 270, and the insulator 271 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
  • the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are preferably in the same plane.
  • the same surface shared by the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 is preferably substantially perpendicular to the substrate.
  • a cross-sectional shape of the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, and the side surfaces of the insulator 270 and the top surface of the oxide 230 may be acute. In that case, the angle formed by the side surfaces of the insulator 250, the conductor 260a, the conductor 260b, and the insulator 270 and the upper surface of the oxide 230 is preferably as large as possible.
  • the post-process may be performed without removing the hard mask (insulator 271) after the processing.
  • the insulator 271 can function as a hard mask even in the addition of a dopant performed in a later step.
  • the above etching may etch an upper portion of a region of the oxide 230b that does not overlap with the insulator 250.
  • the thickness of the region of the oxide 230b that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
  • an insulating film 272A is formed to cover the oxide 230c, the insulator 250, the insulator 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 8).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage.
  • the insulating film 272 ⁇ / b> A having a uniform thickness can be formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the step portion formed by the conductor 260 and the like. it can.
  • anisotropic etching is performed on the insulating film 272A to form the insulator 272 in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270 (see FIG. 9).
  • anisotropic etching process it is preferable to perform a dry etching process.
  • the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.
  • the insulator 270 can remain even if the insulating film 272A over the insulator 270 is removed.
  • the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is higher than the height of the oxide 230a and the oxide 230b, whereby the oxide 230a and the oxide 230 The insulating film 272A on the side surface of 230b can be removed.
  • the time for removing the insulating film 272A formed on the side surfaces of the oxide 230a and the oxide 230b is shortened, which makes it easier.
  • An insulator 272 can be formed.
  • the insulating film 272 ⁇ / b> A may remain on the side surface of the oxide 230. In that case, the film property of an interlayer film formed in a later process can be improved. In addition, since the insulator remains on the side surface of the oxide 230, impurities such as water or hydrogen mixed in the oxide 230 can be reduced, and oxygen can be prevented from being outwardly diffused from the oxide 230. is there.
  • the structure in which the insulating film 272 ⁇ / b> A remains is formed in contact with the side surface of the oxide 230, an insulator 274 containing an element serving as an impurity is formed in a later step, and a region in the oxide 230 is formed.
  • the interface region between the insulator 224 and the oxide 230 is not reduced in resistance, and thus generation of leakage current can be suppressed.
  • indium is added to the oxide 230 so that the oxide 230a has a concentration peak, generation of a leakage current through the oxide 230a can be suppressed.
  • the dopant is added to the oxide 230 through the insulating film 272A.
  • a region 231, a region 232, and a region 234 are formed in the oxide 230.
  • the region 231 and the region 232 are regions obtained by adding metal atoms such as indium and gallium or impurities to the metal oxide provided as the oxide 230. Note that the region 231 has higher conductivity than at least the oxide 230b in the region 234.
  • a metal element such as indium or gallium and a dopant that is at least one of the impurities may be added.
  • the dopant an element that forms oxygen vacancies described above, an element that is trapped by oxygen vacancies, or the like may be used.
  • the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and a rare gas.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • a film containing a dopant may be formed as the insulator 274 in contact with the region 231.
  • an insulating film containing one or more of the above elements is preferably used (see FIG. 10).
  • the insulator 274 including an element that becomes an impurity such as nitrogen is preferably formed in contact with the oxide 230.
  • An insulator containing an element that becomes an impurity such as nitrogen may extract and absorb oxygen contained in the oxide 230 in some cases.
  • oxygen vacancies are generated in the region 231 and the region 232.
  • the oxygen vacancies capture an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 274 by film formation of the insulator 274 or heat treatment after the film formation, so that the regions 231 and 232 have low resistance. Turn into.
  • oxygen vacancies are formed by the added impurity element centering on a region in contact with the insulator 274, and the impurity element further enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. Is done. At that time, it is considered that the impurity is diffused also in the region 232 which is not in contact with the insulator 274, so that the resistance is reduced.
  • the source region and the drain region can be formed in a self-aligned manner by forming the insulator 274. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.
  • the top surfaces and side surfaces of the conductor 260, the insulator 252 and the insulator 250 are covered with the insulator 270 and the insulator 272, so that an impurity element such as nitrogen or hydrogen can be contained in the conductor 260 and the insulator 252. Further, it can be prevented from being mixed into the insulator 250. Thus, an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260, the insulator 252, and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
  • silicon nitride, silicon nitride oxide, or silicon oxynitride formed by a CVD method can be used as the insulator 274.
  • silicon nitride oxide is used as the insulator 274.
  • the region 231a and the region 231b preferably have a higher concentration of at least one of hydrogen and nitrogen than the region 234.
  • the concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • the concentration of hydrogen or nitrogen in the region 234 is set near the center of the region overlapping with the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the region overlapping with the insulator 250 of the oxide 230b).
  • the concentration of hydrogen or nitrogen in a portion where the two are approximately equal may be measured.
  • the region 231, the region 232, and the region 234 are formed using the reduction in resistance of the oxide 230 by forming the insulator 274, but this embodiment is not limited to this. .
  • dopant addition methods include ion implantation method in which ionized source gas is added by mass separation, ion doping method in which ionized source gas is added without mass separation, plasma immersion ion implantation method, etc. Can be used.
  • mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
  • mass separation is not performed, high-concentration ions can be added in a short time.
  • an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
  • the dopant may be added by plasma treatment.
  • plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, or an ashing apparatus, and a dopant can be added to the region 231 and the region 232.
  • the carrier density can be increased and the resistance can be reduced by increasing the content of the above-described elements that form oxygen vacancies and the elements that are trapped by oxygen vacancies.
  • a metal element such as indium is added to increase the content of metal atoms such as indium in the oxide 230, whereby electron mobility can be increased and resistance can be reduced.
  • the atomic ratio of indium to the element M in at least the region 231 is larger than the atomic ratio of indium to the element M in the region 234.
  • the region 232 by increasing the gallium content, diffusion of impurities such as hydrogen added to the region 231 can be suppressed, so that unintended reduction of the execution channel length can be suppressed.
  • the oxide 230 may be subjected to plasma treatment using the insulator 250, the insulator 252, the conductor 260, the insulator 272, the insulator 270, and the insulator 271 as a mask.
  • the plasma treatment may be performed in an atmosphere containing an element that forms oxygen vacancies or an element trapped by oxygen vacancies.
  • plasma treatment may be performed using argon gas and nitrogen gas.
  • the dopant may be added by an ion doping method through the insulating film 272A.
  • the insulating film 272A is provided to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 270. Therefore, in the direction perpendicular to the top surface of the oxide 230, the thickness of the insulating film 272A differs in the periphery of the side surfaces of the insulator 250, the conductor 260, and the insulator 270 and in other regions.
  • the thickness of the insulating film 272A is larger in the vicinity of the side surfaces of the insulator 250, the conductor 260, and the insulator 270 than in other regions. That is, by adding a dopant through the insulating film 272A, the region 231 and the region 232 can be provided in a self-aligned manner even in a transistor whose channel length is reduced to about 10 nm to 30 nm.
  • the region 232 may be formed by diffusion of the dopant in the region 231 in a process such as a heat treatment performed in a later process.
  • the region 232 since the region 232 is provided, a high-resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; thus, on-state current and mobility of the transistor Can be increased.
  • the region 232 since the region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed.
  • leakage current at the time of non-conduction can be reduced.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the added dopant diffuses into the region 232 of the oxide 230, so that the on-state current can be increased.
  • the insulator 280 is formed over the insulator 274.
  • the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.
  • silicon oxynitride is used as the insulating film.
  • the insulator 280 is preferably formed so that the upper surface has flatness.
  • the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280.
  • the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process.
  • the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.
  • an opening reaching the region 231a of the oxide 230 and an opening reaching the region 231b of the oxide 230 are formed in the insulator 280 and the insulator 274.
  • the opening may be formed using a lithography method. Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 240a and the conductor 240b are provided in contact with the side surface of the oxide 230.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a semiconductor device including the transistor 200 can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device of this embodiment illustrated in FIGS.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • FIG. 12A, 13A, and 14A are top views of a semiconductor device including a transistor 200.
  • FIG. 12B, 12C, 13B, 13C, 14B, and 14C are cross-sectional views of the semiconductor device.
  • FIG. 12B, FIG. 13B, or FIG. 14B is shown by a one-dot chain line in FIG. 12A, FIG. 13A, or FIG. 2 is a cross-sectional view of a portion, and is also a cross-sectional view of the transistor 200 in a channel length direction.
  • FIG. 12C, FIG. 13C, or FIG. 14C is the portion indicated by the one-dot chain line A3-A4 in FIG. 12A, FIG. 13A, or FIG. 2 is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIGS. 12A, 13A, and 14A some elements are omitted for clarity.
  • the structure of the transistor 200 will be described with reference to FIGS. 12, 13A, and 14A, respectively.
  • the material described in detail in ⁇ Structure example of semiconductor device> can be used as the constituent material of the transistor 200.
  • a transistor 200 illustrated in FIG. 12 is different from the semiconductor device illustrated in ⁇ Structure Example of Semiconductor Device> in that it includes at least an insulator 273.
  • an insulator 273 is provided between the insulator 224, the oxide 230, the insulator 272, and the insulator 271 and the insulator 274.
  • the thickness and material of the insulator 273 may be appropriately designed depending on the required transistor performance.
  • the insulator 273 an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used.
  • impurities such as water or hydrogen and oxygen
  • aluminum oxide or hafnium oxide is preferably used. Accordingly, the thickness of the insulator 273 can be reduced. Specifically, the thickness of the insulator 273 is preferably 0.5 nm or more and 1.2 nm or less.
  • the insulator 273 is preferably formed by an ALD method. By using the ALD method, the insulator 273 with high film property can be formed.
  • an insulator having a function of suppressing transmission of impurities such as water or hydrogen and oxygen and covering the side surface of the insulator 272 enhances the barrier property of the insulator 272. be able to. Accordingly, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260, the insulator 250, and the insulator 252. Therefore, the insulator 273 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.
  • a transistor 200 illustrated in FIG. 13 is different from the semiconductor device illustrated in ⁇ Structure Example of Semiconductor Device> at least in shape of an oxide 230c.
  • the oxide 230c is provided to cover the oxide 230a and the oxide 230b. That is, the oxide 230b is surrounded by the oxide 230a and the oxide 230c. With this structure, entry of impurities into the oxide 230b in which a channel is formed in the region 234 can be suppressed.
  • the side surface of the oxide 230a and the side surface of the oxide 230b are preferably provided so as to be on the same plane.
  • the oxide 230c is preferably formed so as to cover the oxide 230a and the oxide 230b.
  • the oxide 230c is formed in contact with a side surface of the oxide 230a, a top surface and a side surface of the oxide 230b, and a part of the top surface of the insulator 224.
  • the side surfaces of the oxide 230c are located outside the side surfaces of the oxide 230a and the oxide 230b.
  • a transistor 200 illustrated in FIGS. 14A to 14C has a plurality of channel formation regions with respect to one gate electrode, which is different from the structure of the transistor 200 illustrated in FIGS. Since the transistor 200 includes a plurality of channel formation regions, a large on-state current can be obtained. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-state current can be obtained in each channel formation region.
  • FIG. 14 shows an example having three channel formation regions, the number of channel formation regions is not limited to this. For other structures, the structure of the transistor 200 illustrated in FIGS. 1A, 1B, and 1C is referred to.
  • ⁇ Configuration example of semiconductor device> 15A, 15B, and 15C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.
  • FIG. 15A is a top view of a cell 600 including the transistor 200 and the capacitor 100.
  • 15B and 15C are cross-sectional views of the cell 600.
  • FIG. 15B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 15A and also a cross-sectional view in the channel length direction of the transistor 200.
  • FIG. 15C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 15A and is a cross-sectional view in the channel width direction of the transistor 200.
  • some elements are omitted for clarity.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 functioning as an interlayer film.
  • a conductor 240 (a conductor 240a, a conductor 240b, a conductor 240c, and a conductor 240d) that is electrically connected to the transistor 200 and functions as a plug is included.
  • the transistor 200 and the capacitor 100 are provided in the same layer, so that part of the structure included in the transistor 200 is used in combination with part of the structure included in the capacitor 100. be able to. That is, part of the structure of the transistor 200 may function as part of the structure of the capacitor 100.
  • the capacitor 200 when the capacitor 200 is partially or entirely overlapped with the transistor 200, the total area of the projected area of the transistor 200 and the projected area of the capacitor 100 can be reduced.
  • a conductor 240b that functions as a plug or a wiring electrically connected to the transistor 200 and a conductor 207 (the conductor 207a and the conductor 207b) are provided below the region where the capacitor 100 and the transistor 200 overlap with each other.
  • the cell 600 can be easily miniaturized or highly integrated.
  • the conductor 207 can be formed in the same process as the conductor 205 which is the structure of the transistor 200, the process can be shortened.
  • the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on the capacitance value required for the capacitor 100.
  • the area of the capacitor 100 is determined by the area where the region 231 b of the oxide 230 overlaps with the conductor 120 with the insulator 130 interposed therebetween. Therefore, when the capacitance value necessary for the cell 600 cannot be obtained with the capacitor 100 illustrated in FIGS. 15A and 15B, the width in the A3-A4 direction in the region 231b of the oxide 230a and the oxide 230b Can be made larger than the width in the A3-A4 direction in the region 234 of the oxide 230a and the oxide 230b, whereby the capacitance value can be increased.
  • the length in the A1-A2 direction in the region 231b of the oxide 230 may be larger than the length in the A1-A2 direction in the conductor 120.
  • the conductor 240b can be embedded in the insulator 280. That is, the oxide 230 region 231b and the conductor 240b may be provided in contact with each other in a region where the oxide 230 region 231b and the conductor 120 do not overlap. Therefore, the process can be shortened by forming the conductor 240a, the conductor 240b, and the conductor 240c in the same process.
  • the transistor 200 is formed in the same process as the capacitor 100. Therefore, since the process can be shortened, productivity can be improved.
  • Transistor 200 As the transistor 200, the transistor structure included in the semiconductor device described in the above embodiment may be used.
  • the transistor 200 illustrated in FIGS. 15A and 15B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the capacitor 100 has a structure in common with the transistor 200.
  • the region 231 b provided in the oxide 230 of the transistor 200 is described as an example of the capacitor 100 that functions as one of the electrodes of the capacitor 100.
  • the capacitor 100 includes a region 231b of the oxide 230, the insulator 130 over the region 231b, and the conductor 120 over the insulator 130.
  • the conductor 120 is preferably provided over the insulator 130 so that at least a part thereof overlaps with the region 231 b of the oxide 230.
  • the region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 functions as the other of the electrodes of the capacitor 100.
  • the insulator 130 functions as a dielectric of the capacitor element 100.
  • the region 231b of the oxide 230 has a reduced resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.
  • the insulator 130 may be provided by processing the insulator 274.
  • the insulator 130 (the insulator 274) may remain in contact with the transistor 200 and the insulator 224.
  • the insulator 274 may not be provided and the insulator 130 may be separately provided as a dielectric.
  • the insulator 130 for example, aluminum oxide or silicon oxynitride may be used in a single layer or a stacked layer.
  • the conductor 120 is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. Although not shown, the conductor 120 may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material.
  • the cell array can be formed by arranging the transistor 200 including the transistor 200 and the capacitor 100 illustrated in FIG. 15 in a matrix or a matrix.
  • FIG. 16A is a circuit diagram illustrating an embodiment in which the cells 600 illustrated in FIG. 15 are arranged in a matrix.
  • one of a source and a drain of a transistor included in a cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03).
  • the BL is also electrically connected to one of a source and a drain of a transistor included in a cell arranged in the column direction.
  • the first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06).
  • the transistor included in each cell 600 may be provided with the second gate BG.
  • the threshold value of the transistor can be controlled by the potential applied to BG.
  • the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor.
  • the second electrode of the capacitor included in the cell 600 is electrically connected to the power supply line PL.
  • FIG. 16B illustrates a circuit 610 including the cell 600a electrically connected to WL04 and BL02 and the cell 600b electrically connected to WL03 and BL02 as part of the row in FIG. It is sectional drawing extracted.
  • FIG. 16B is a cross-sectional view of the cell 600a and the cell 600b.
  • the cell 600a includes a transistor 200a and a capacitor 100a.
  • the cell 600b includes a transistor 200b and a capacitor 100b.
  • One of a source and a drain of the transistor 200a and one of a source and a drain of the transistor 200b are both electrically connected to BL02.
  • the occupied area of the cell array can be further reduced.
  • FIG. 17A is a circuit diagram showing a mode different from FIG. 16A in a circuit in which the cells 600 shown in FIG. 15 are arranged in a matrix.
  • a first gate of a transistor included in the cell 600 arranged in the row direction is electrically connected to a common WL (WL01, WL02, WL03).
  • one of a source and a drain of a transistor included in a cell arranged in the column direction is electrically connected to a common BL (BL01 to BL06).
  • the transistor included in each cell 600 may be provided with the second gate BG.
  • the threshold value of the transistor can be controlled by the potential applied to BG.
  • the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be formed of a part of a structure forming the transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to the PL.
  • FIG. 17B illustrates a circuit 610 including the cell 600a electrically connected to WL02 and BL03 and the cell 600b electrically connected to WL02 and BL04 as part of the row in FIG. 17A. It is sectional drawing extracted.
  • FIG. 17B is a cross-sectional view of the cell 600a and the cell 600b.
  • the cell 600a includes a transistor 200a and a capacitor 100a.
  • the cell 600b includes a transistor 200b and a capacitor 100b.
  • the memory device illustrated in FIGS. 18 and 19 includes the transistor 300, the transistor 200, and the capacitor 100.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 18 and FIG. 19 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is applied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing).
  • predetermined charge is given to the gate of the transistor 300 (writing).
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
  • the wiring 1002 takes a potential corresponding to the amount of charge held in the node FG.
  • the apparent threshold voltage V th_H when the gate of the transistor 300 is supplied with a high level charge is the low level charge applied to the gate of the transistor 300.
  • the apparent threshold voltage refers to the potential of the wiring 1005 necessary for bringing the transistor 300 into a “conductive state”.
  • the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is in a “conducting state” when the potential of the wiring 1005 is V 0 (> V th_H ). On the other hand, in the case where a low-level charge is supplied to the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the wiring 1005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the wiring 1002, information held in the node FG can be read.
  • the memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • transistor 300 illustrated in FIGS. 18A and 18B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
  • the insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • the insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
  • TDS temperature programmed desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is calculated by converting the amount of desorption converted to hydrogen atoms per area of the insulator 324 in the range of the surface temperature of the film from 50 ° C. to 500 ° C. in TDS analysis. 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer.
  • a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324.
  • the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen.
  • tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 354 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
  • a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 370.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked.
  • a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
  • the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen.
  • An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
  • the insulator 210 and the insulator 214 are each formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.
  • the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212 and the insulator 216.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like.
  • the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300.
  • the conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 200 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.
  • a transistor 200 is provided above the insulator 216. Note that as the transistor 200, the transistor structure of the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIGS. 18A and 18B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • An insulator 280 is provided above the transistor 200.
  • An insulator 282 is provided over the insulator 280.
  • the insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214.
  • the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.
  • An insulator 286 is provided over the insulator 282.
  • the insulator 286 can be formed using a material similar to that of the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.
  • a conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 274, the insulator 280, the insulator 282, and the insulator 286.
  • the conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the capacitor element 100 is provided above the transistor 200.
  • the capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.
  • the conductor 112 may be provided over the conductor 246 and the conductor 248.
  • the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 110 has a function as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.
  • the conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component.
  • a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium or a metal nitride film containing the above-described element as a component.
  • titanium nitride film, molybdenum nitride film, tungsten nitride film or the like can be used.
  • indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 112 and the conductor 110 have single-layer structures; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used.
  • a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • an insulator 130 is provided as a dielectric of the capacitor 100 over the conductor 112 and the conductor 110.
  • the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination
  • the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor element 100 has improved dielectric strength and can suppress electrostatic breakdown of the capacitor element 100.
  • a conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110.
  • the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.
  • An insulator 150 is provided over the conductor 120 and the insulator 130.
  • the insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.
  • a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • a transistor including an oxide semiconductor with high on-state current can be provided.
  • a transistor including an oxide semiconductor with low off-state current can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • FIG. 19 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. Note that in the memory device illustrated in FIG. 19, the structure having the same function as that of the semiconductor device and the structure of the memory device described in the above embodiment and ⁇ Structure of the memory device 1> are denoted by the same reference numerals. To do.
  • a transistor 200 illustrated in FIG. 19 is different from the semiconductor device illustrated in ⁇ Structure example of the memory device 1> in that the cell 600 described in the above embodiment is provided.
  • a cell 600 sharing a part of the structure of the capacitor 100 and a part of the structure of the transistor 200.
  • the cell 600 can be easily miniaturized or highly integrated.
  • the process can be shortened.
  • the semiconductor device illustrated in FIG. 20 is a memory device including the transistor 400, the transistor 200, and the capacitor 100.
  • a storage device will be described with reference to FIG.
  • FIG. 20A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment.
  • FIG. 20B is a cross-sectional view of the semiconductor device in which the wiring 1003 to the wiring 1010 shown in FIG.
  • the transistor 200 has a gate electrically connected to the wiring 1004, one of a source and a drain is electrically connected to the wiring 1003, and the other of the source and the drain is electrically connected to one of the electrodes of the capacitor 100.
  • the other electrode of the capacitor 100 is electrically connected to the wiring 1005.
  • the drain of the transistor 400 is electrically connected to the wiring 1010.
  • the second gate of the transistor 200 and the source, first gate, and second gate of the transistor 400 are a wiring 1006, a wiring 1007, a wiring 1008, and a wiring 1009. It is electrically connected via.
  • the on state and the off state of the transistor 200 can be controlled.
  • the transistor 200 is turned on and a potential is applied to the wiring 1003
  • electric charge can be supplied to the capacitor 100 through the transistor 200.
  • the charge supplied to the capacitor 100 can be held by turning off the transistor 200.
  • the wiring 1005 can be controlled to have a potential at a connection portion between the transistor 200 and the capacitor 100 by capacitive coupling by applying an arbitrary potential. For example, when the ground potential is applied to the wiring 1005, the charge is easily held.
  • a negative potential is applied to the second gate of the transistor 200 through the transistor 400, the threshold voltage of the transistor 200 is made higher than 0 V, and the off-state current is reduced. It is possible to reduce the drain current when the first gate voltage is 0V.
  • the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected to each other.
  • the gate voltage can be controlled.
  • the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source are 0V.
  • the first gate voltage of the transistor 400 is 0 V, the drain current is very small and the threshold voltage is higher than that of the transistor 200. With this configuration, the transistor 200 can be supplied without supplying power to the transistor 400.
  • the negative potential of the second gate can be maintained for a long time.
  • the drain current when the first gate voltage of the transistor 200 is 0 V can be extremely reduced without supplying power to the transistor 200. it can. That is, electric charge can be held in the capacitor 100 for a long time without supplying power to the transistor 200 and the transistor 400.
  • a semiconductor device as a memory element, long-term memory retention can be performed without power supply. Therefore, a memory device that has a low refresh operation frequency or does not require a refresh operation can be provided.
  • connection relation of the transistor 200, the transistor 400, and the capacitor 100 is not limited to that illustrated in FIGS.
  • the connection relationship can be changed as appropriate according to the required circuit configuration.
  • FIG. 20B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device illustrated in FIG. 20, the structure having the same function as the structure of the semiconductor device and the memory device described in the above embodiment and ⁇ Structure of the memory device 1> is denoted by the same reference numeral. To do.
  • a memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 300 and the transistor 200.
  • capacitor 100 and the transistor 200 the capacitor and the transistor included in the semiconductor device and the memory device described in any of the above embodiments and FIGS. 18 and 19 may be used.
  • the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIGS. 20A and 20B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
  • the transistor 400 includes a conductor 460 (a conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 (a conductor 405a and a conductor 405b) that functions as a second gate electrode,
  • the insulator 470 and the insulator 472 which are in contact with the conductor 460, the insulator 220 which functions as a gate insulating layer, the insulator 222, the insulator 224, and the insulator 450, and an oxide 430c including a region where a channel is formed
  • an oxide 431a and an oxide 431b which function as one of a source or a drain and an oxide 432a and an oxide 432b which function as the other of a source or a drain.
  • the conductor 405 functioning as the second gate electrode is electrically connected to the conductor 403 (conductors 403a and 403b
  • the conductor 405 is the same layer as the conductor 205.
  • the oxide 431a, the oxide 432a, and the oxide 230a are the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are the same layer.
  • the oxide 430c is the same layer as the oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the insulator 452 is the same layer as the insulator 252.
  • the conductor 460 is the same layer as the conductor 260.
  • the insulator 470 is the same layer as the insulator 270.
  • the insulator 472 is the same layer as the insulator 272.
  • the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely reduced.
  • a semiconductor device including a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor.
  • miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.
  • a miniaturized or highly integrated semiconductor device can be provided with high productivity.
  • the semiconductor device illustrated in FIG. 21 is a memory device including the transistor 400, the transistor 300, the transistor 200, and the capacitor 100.
  • a memory device including the transistor 400, the transistor 300, the transistor 200, and the capacitor 100.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. Since the transistor described in any of the above embodiments can be formed with high yield even when miniaturized, the transistor 200 can be miniaturized. By using such a transistor for a memory device, the memory device can be miniaturized or highly integrated. Since the off-state current of the transistor described in any of the above embodiments is small, stored data can be held for a long time by using it for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is connected to the drain of the transistor 400. And are electrically connected.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the semiconductor device illustrated in FIG. 21 has the characteristic that the potential of the gate of the transistor 300 can be held; thus, information can be written, held, and read as described below.
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is applied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing).
  • predetermined charge is given to the gate of the transistor 300 (writing).
  • the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
  • the wiring 1002 takes a potential corresponding to the amount of charge held in the node FG.
  • the apparent threshold voltage V th_H when the gate of the transistor 300 is supplied with a high level charge is the low level charge applied to the gate of the transistor 300.
  • the apparent threshold voltage refers to the potential of the wiring 1005 necessary for bringing the transistor 300 into a “conductive state”.
  • the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is in a “conducting state” when the potential of the wiring 1005 is V 0 (> V th_H ). On the other hand, in the case where a low-level charge is supplied to the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the wiring 1005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the wiring 1002, information held in the node FG can be read.
  • FIG. 21 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. Note that the memory device in FIG. 21 has the same function as the structure of the semiconductor device and the memory device described in the above embodiment, ⁇ Structure of the memory device 1>, and ⁇ Structure of the memory device 2>. The same symbols are added to the structures having the same.
  • the memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.
  • capacitor 100, the transistor 200, the transistor 300, and the transistor 400 the capacitors and transistors included in the semiconductor device and the memory device described in any of the above embodiments and FIGS.
  • the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIGS. 21A and 21B are examples, and the structure is not limited thereto, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • a semiconductor device including a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor.
  • miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.
  • a miniaturized or highly integrated semiconductor device can be provided with high productivity.
  • a memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.
  • the memory device illustrated in FIG. 22 is a semiconductor device that forms a memory cell array by arranging the memory devices illustrated in FIGS. 18 and 21 in a matrix. Note that one transistor 400 can control the back gate voltage of the plurality of transistors 200. Therefore, the transistor 400 is preferably provided in a smaller number than the transistor 200.
  • FIG. 22 is a cross-sectional view of a part of rows in the case where the storage devices shown in FIGS. 18 and 21 are arranged in a matrix.
  • FIG. 22 is different from FIG. 21 in the structure of the transistor 300.
  • a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape.
  • a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween.
  • the conductor 316 may be formed using a material that adjusts a work function.
  • Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate.
  • an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
  • the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • a memory cell 650a and a memory cell 650b are arranged adjacent to each other.
  • the memory cell 650a and the memory cell 650b each include the transistor 300, the transistor 200, and the capacitor 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006.
  • a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is a node FG.
  • the wiring 1002 is a wiring common to the adjacent memory cells 650a and 650b.
  • a semiconductor device including a transistor including an oxide semiconductor variation in electrical characteristics can be suppressed and reliability can be improved.
  • power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor.
  • miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.
  • a miniaturized or highly integrated semiconductor device can be provided with high productivity.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • 2T type, 3T type gain cell type
  • OS memory a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied.
  • the OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 23 shows a configuration example of NOSRAM.
  • a NOSRAM 1600 illustrated in FIG. 23 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
  • the memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • one memory cell 1611 stores 3-bit (eight values) data.
  • the controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0].
  • the controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to be accessed.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • the column driver 1660 drives the source line SL and the bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
  • FIG. 24A is a circuit diagram illustrating a structural example of the memory cell 1611.
  • the memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor.
  • the capacitive element C61 is a holding capacitor for holding the voltage of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • bit line is a common bit line for writing and reading, but a writing bit line WBL and a reading bit line RBL may be provided as shown in FIG. Good.
  • FIGS. 24C to 24E show other configuration examples of the memory cell.
  • FIGS. 24C to 24E show an example in which a write bit line and a read bit line are provided. As shown in FIG. 24A, bit lines shared by writing and reading are shown. May be provided.
  • a memory cell 1612 shown in FIG. 24C is a modification example of the memory cell 1611 and is obtained by changing a reading transistor to an n-channel transistor (MN61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • the OS transistor MO61 may be an OS transistor without a back gate.
  • a memory cell 1613 illustrated in FIG. 24D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • a memory cell 1614 shown in FIG. 24E is a modification example of the memory cell 1613, in which the reading transistor and the selection transistor are changed to n-channel transistors (MN62 and MN63).
  • the transistors MN62 and MN63 may be OS transistors or Si transistors.
  • the OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.
  • the NOSRAM 1600 Since data is rewritten by charging / discharging the capacitive elements C61 and C62, the NOSRAM 1600 has no limitation on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
  • the transistor 200 is used as the OS transistors MO61 and MO62
  • the capacitor 100 is used as the capacitors C61 and C62
  • the transistors MP61 and MN62 are used.
  • the transistor 300 can be used.
  • the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated.
  • the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS.
  • DOSRAM registered trademark
  • OS memory is applied to DOSRAM as well as NOSRAM.
  • FIG. 25 shows a configuration example of the DOSRAM.
  • the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
  • MC-SA array 1420 a sense amplifier array 1420
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • Global bit lines GBLL and GBLR are stacked on the memory cell array 1422.
  • a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
  • the memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> -1425 ⁇ N-1>.
  • FIG. 26A illustrates a configuration example of the local memory cell array 1425.
  • the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 26B illustrates a circuit configuration example of the memory cell 1445.
  • the memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2.
  • the transistor MW1 has a function of controlling charging / discharging of the capacitor CS1.
  • the gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitor.
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant voltage (for example, a low power supply voltage) is input to the terminal B2.
  • the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1.
  • the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated.
  • the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • the transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage at the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B1 may be changed according to the operation of the DOSRAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.
  • the sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> -1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to the sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference.
  • the switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
  • bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier.
  • a global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form one bit line pair.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
  • the controller 1405 has a function of controlling the overall operation of the DOSRAM 1400.
  • the controller 1405 performs a logical operation on a command signal input from the outside to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. It has a function of holding an address signal input from the outside and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of deloading an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
  • a column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column.
  • the switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413.
  • the plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
  • the column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • the global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference.
  • Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.
  • Data is written to the global bit line pair by the input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
  • One row of the local memory cell array 1425 is designated by the address signal.
  • the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line.
  • the local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data.
  • the switch array 1444 writes the data in the column specified by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair.
  • the global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
  • the DOSRAM 1400 Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
  • the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.
  • the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.
  • an FPGA field programmable gate array
  • OS-FPGA field programmable gate array
  • FIG. 27A illustrates a configuration example of the OS-FPGA.
  • the OS-FPGA 3110 illustrated in FIG. 27A is capable of context switching by a multi-context structure, fine-grain power gating, and NOFF (normally off) computing.
  • the OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
  • the programmable area 3115 includes two input / output blocks (IOB) 3117 and a core (Core) 3119.
  • the IOB 3117 has a plurality of programmable input / output circuits.
  • the core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130.
  • the LAB 3120 has a plurality of programmable logic elements (PLE) 3121.
  • FIG. 27B shows an example in which the LAB 3120 is configured with five PLE 3121s.
  • the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array.
  • the LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
  • Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship.
  • the number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal.
  • the signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
  • the SB 3131 includes PRSs (programmable routing switches) 3133 [0] and 3133 [1].
  • the PRSs 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
  • FIG. 28B illustrates a circuit configuration example of the PRS 3133 [0].
  • PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration.
  • PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal.
  • the signals context [0] and word [0] are input to the PRS 3133 [0]
  • the signals context [1] and word [1] are input to the PRS 3133 [1].
  • the signal context [0] becomes “H”
  • the PRS 3133 [0] becomes active.
  • the PRS 3133 [0] includes a CM 3135 and a Si transistor M31.
  • the Si transistor M31 is a pass transistor controlled by the CM 3135.
  • the CM 3135 includes memory circuits 3137 and 3137B.
  • the memory circuits 3137 and 3137B have the same circuit configuration.
  • the memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32.
  • the memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.
  • the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitor 100 can be used as the capacitors C31 and CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.
  • the gate of the Si transistor M31 is the node N31
  • the gate of the OS transistor MO32 is the node N32
  • the gate of the OS transistor MOB32 is the node NB32.
  • Nodes N32 and NB32 are charge holding nodes of the CM 3135.
  • the OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0].
  • the OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.
  • Data held in the memory circuits 3137 and 3137B has a complementary relationship. Therefore, either one of the OS transistors MO32 or MOB32 becomes conductive.
  • the PRS 3133 [0] While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
  • the PRS 3133 [0] is active.
  • the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
  • the OS transistor MO32 of the memory circuit 3137 is a source follower, and thus the gate voltage of the Si transistor M31 increases due to boosting. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
  • the CM 3135 also has a multiplexer function.
  • FIG. 29 shows a configuration example of PLE 3121.
  • the PLE 3121 includes a lookup table block (LUTblock) 3123, a register block 3124, a selector 3125, and a CM 3126.
  • the LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the inputs inA-inD.
  • the selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration stored in the CM 3126.
  • the PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
  • the register block 3124 is configured by a nonvolatile register.
  • the nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.
  • the register block 3124 includes OS-FFs 3140 [1] 3140 [2]. Signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2].
  • the clock signal CLK1 is input to the OS-FF 3140 [1]
  • the clock signal CLK2 is input to the OS-FF 3140 [2].
  • FIG. 30A illustrates a configuration example of the OS-FF 3140.
  • the OS-FF 3140 includes an FF 3141 and a shadow register 3142.
  • the FF 3141 includes nodes CK, R, D, Q, and QB.
  • a clock signal is input to the node CK.
  • a signal user_res is input to the node R.
  • the signal user_res is a reset signal.
  • Node D is a data input node
  • node Q is a data output node.
  • Nodes Q and QB have a complementary logic relationship.
  • the shadow register 3142 functions as a backup circuit for the FF 3141.
  • the shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
  • the shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B.
  • the memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133.
  • the memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36.
  • the memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36.
  • Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, respectively, and are charge holding nodes.
  • Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.
  • the transistor 200 can be used as the OS transistors MO35 and MOB35, and the capacitor 100 can be used as the capacitors C36 and CB36. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.
  • the shadow register 3142 backs up the data in the FF 3141.
  • the node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 holds the backed up data even when the power is turned off.
  • the power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
  • the power consumption of the OS-FPGA 3110 can be effectively reduced.
  • An error that may occur in the memory circuit is a soft error due to the incidence of radiation.
  • a soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair.
  • An OS memory using an OS transistor has high soft error resistance. Therefore, the OS-FPGA 3110 with high reliability can be provided by installing the OS memory.
  • FIG. 31 is a block diagram illustrating a configuration example of the AI system 4041.
  • the AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.
  • the arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014.
  • DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.
  • the control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access MemoryPROM 40 Memory, Memory Memory 4024).
  • the input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.
  • the arithmetic unit 4010 can execute learning or inference using a neural network.
  • the analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
  • the analog arithmetic circuit 4011 is preferably formed using an OS transistor.
  • An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021.
  • the DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • the input data may exceed 1000.
  • the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions.
  • the DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.
  • a NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.
  • the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit.
  • the analog data refers to data having a resolution of 3 bits (8 values) or more.
  • the multi-value data described above may be included in the analog data.
  • Data and parameters used for calculation of the neural network can be temporarily stored in the NOSRAM 4013.
  • the data and parameters may be stored in the memory provided outside the AI system 4041 via the CPU 4021.
  • the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.
  • the FPGA 4014 is an FPGA using an OS transistor.
  • the AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM).
  • a neural network connection such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can reduce the area of the memory compared to the FPGA configured with SRAM. Therefore, even if a context switching function is added, the area increase is small.
  • the OS-FPGA can transmit data and parameters at high speed by boosting.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.
  • the AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed.
  • the PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.
  • the AI system 4041 preferably includes a GPU 4022.
  • the AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog calculation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.
  • the PLL 4023 has a function of generating a clock.
  • the AI system 4041 operates based on the clock generated by the PLL 4023.
  • the PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.
  • the AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM.
  • the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.
  • Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.
  • the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
  • the AI system 4041 includes an audio codec 4032 and a video codec 4033.
  • the audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).
  • the AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.
  • the analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory.
  • the flash memory has a limited number of rewritable times.
  • it is very difficult to form a multi-level flash memory in an embedded manner an arithmetic circuit and a memory are formed on the same die.
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy.
  • circuit design for separating data writing and reading becomes complicated.
  • the analog arithmetic circuit 4011 may use MRAM as an analog memory.
  • MRAM has a low resistance change rate and has a problem in terms of storage accuracy.
  • the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.
  • FIG. 32A shows an AI system 4041A in which the AI systems 4041 described in FIG. 31 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.
  • An AI system 4041A illustrated in FIG. 32A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number).
  • the AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.
  • FIG. 32B shows an AI system 4041B in which the AI system 4041 described in FIG. 31 is arranged in parallel as in FIG. 32A, and signals can be transmitted and received between systems via a network. is there.
  • An AI system 4041B illustrated in FIG. 32B includes a plurality of AI systems 4041_1 to 4041_n.
  • the AI systems 4041_1 to 4041_n are connected to each other via a network 4099.
  • the network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
  • the communication module can communicate via an antenna.
  • the Internet Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (Campure Area Network, MAN (MetropoliAwareNetwork), MAN (MetropoliAureNetwork), which are the foundations of the World Wide Web (WWW).
  • Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication.
  • LTE Long Term Evolution
  • GSM Global System for Mobile Communication: registered trademark
  • EDGE Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Emulsion
  • Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.
  • analog signals obtained by an external sensor or the like can be processed by separate AI systems.
  • information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information
  • various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor
  • analog signals can be processed by separate AI systems. it can.
  • the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.
  • the AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.
  • FIG. 33 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 illustrated in FIG. 33 includes a lead 7001 and a circuit portion 7003.
  • the AI system IC 7000 is mounted on a printed circuit board 7002, for example.
  • a plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004).
  • the circuit portion 7003 is provided with the various circuits described in the above embodiment in one die.
  • the circuit portion 7003 has a stacked structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.
  • QFP Quad Flat Package
  • a digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and OS memories such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.
  • the semiconductor device according to one embodiment of the present invention can be used for various electronic devices.
  • FIG. 34 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
  • FIG. 34A is an external view illustrating an example of an automobile.
  • the automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.
  • the automobile 2980 includes an antenna, a battery, and the like.
  • An information terminal 2910 illustrated in FIG. 34B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
  • the display portion 2912 includes a display panel using a flexible substrate and a touch screen.
  • the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
  • the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
  • a laptop personal computer 2920 illustrated in FIG. 34C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
  • the laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
  • a video camera 2940 illustrated in FIG. 34D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like.
  • the operation switch 2944 and the lens 2945 are provided on the housing 2941
  • the display portion 2944 is provided on the housing 2942.
  • the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941.
  • the housing 2941 and the housing 2942 are connected to each other by a connection portion 2946.
  • the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946.
  • the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
  • FIG. 34E illustrates an example of a bangle information terminal.
  • the information terminal 2950 includes a housing 2951, a display portion 2952, and the like.
  • the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951.
  • the display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.
  • FIG. 34F illustrates an example of a wristwatch type information terminal.
  • the information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like.
  • the information terminal 2960 includes an antenna, a battery, and the like inside the housing 2961.
  • the information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.
  • the display surface of the display portion 2962 is curved, and display can be performed along the curved display surface.
  • the display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like.
  • an application can be started by touching an icon 2967 displayed on the display unit 2962.
  • the operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. .
  • the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.
  • the information terminal 2960 can execute short-range wireless communication based on a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.
  • a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period.
  • a highly reliable electronic device can be realized.
  • the density, crystallinity, and flatness of the hafnium oxide film formed by a sputtering method were analyzed.
  • the flatness was measured and observed using an atomic force microscope (AFM).
  • the crystallinity was analyzed using X-ray diffraction (XRD: X-Ray Diffraction).
  • Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, Sample 1F, Sample 1G, and Sample 1H were prepared and analyzed.
  • FIG. 35 shows a laminated structure of each sample.
  • Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, Sample 1F, Sample 1G, and Sample 1H are a substrate 910, an insulator 912 on the substrate 910, and an insulator 914 on the insulator 912, respectively.
  • the following table shows the film formation temperature of the insulator 914 in the samples 1A to 1H.
  • a silicon wafer was prepared as the substrate 910.
  • a silicon oxide film having a thickness of 100 nm was formed as the insulator 912 over the substrate 910 by a thermal oxidation method.
  • a hafnium oxide film with a thickness of 5 nm was formed as the insulator 914 over the insulator 912 using a sputtering apparatus.
  • the hafnium oxide film is formed using a hafnium oxide target in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) or in an oxygen (O 2 ) atmosphere, at a pressure of 0.7 Pa, and the target and the substrate.
  • RF power
  • FIG. 36 shows bright-field images (hereinafter also referred to as TEM images) of Sample 1A to Sample 1H, which are obtained by a scanning transmission electron microscope (STEM: Scanning Transmission Electron Microscope).
  • STEM scanning transmission electron microscope
  • the TEM image was acquired using a scanning transmission electron microscope HD-2700 manufactured by Hitachi High-Technologies Corporation, with an acceleration voltage of 200 kV and a beam diameter of about 0.4 nm ⁇ .
  • FIG. 36 shows that when the oxygen flow rate ratio is the same, the higher the film formation temperature, the higher the crystallinity. Further, FIG. 36 shows that when the film formation temperature is the same, the film flatness tends to be increased by performing the film formation in a mixed atmosphere containing oxygen.
  • the insulator 914 of the sample 1E and the sample 1F it was observed that a shape having a recess or a protrusion was formed between one of the crystal regions and another crystal region or an amorphous region. . Further, the interface between the insulator 912 and the insulator 914 was observed in a state of being less clear than the sample 1A or the sample 1B. The shape is considered to be due to the fact that the surface of the film is raised and the flatness of the film is lowered when each crystal region grows. Further, when Samples 1E to 1H were compared, it was observed that as the film formation temperature was closer to 150 ° C., one of the crystal regions tended to be larger and the film surface had less unevenness.
  • the insulator 914 of Samples 1A to 1D has a flat film surface.
  • the interface between the insulator 912 and the insulator 914 was clearly observed.
  • the root mean square roughness (RMS) of Sample 1A was 2.5 ⁇ 10 ⁇ 1 nm (before heating).
  • Sample 1D had a root mean square roughness (RMS) of 2.9 ⁇ 10 ⁇ 1 nm (before heating).
  • Sample 1E had a root mean square roughness (RMS) of 4.3 ⁇ 10 ⁇ 1 nm (before heating).
  • Sample 1H had a root mean square roughness (RMS) of 4.7 ⁇ 10 ⁇ 1 nm (before heating).
  • Sample 1A and Sample 1D have higher flatness than Sample 1E and Sample 1H. Therefore, it was found that a hafnium oxide film using a sputtering method can be formed in a mixed atmosphere containing oxygen to form a film with high flatness.
  • the hafnium oxide film using the sputtering method has a root mean square roughness (RMS) of 0.40 nm or less in a measurement range of 1 ⁇ m ⁇ 1 ⁇ m by appropriately setting the deposition conditions. It was.
  • RMS root mean square roughness
  • a circular (ring-shaped) pattern may be observed.
  • a circular (ring-shaped) pattern is observed even for a substance having a microcrystal close to an amorphous structure depending on measurement conditions such as a beam diameter used (for example, an electron beam having a beam diameter of about 50 nm ⁇ or more). There is a case.
  • a beam diameter used for example, an electron beam having a beam diameter of about 50 nm ⁇ or more.
  • FIG. 38 shows the results of acquiring electron diffraction patterns of Sample 1A, Sample 1D, Sample 1E, and Sample 1H.
  • Sample 1A is an electron beam diffraction pattern at a point A shown in the cross-sectional TEM image
  • sample 1D is an electron beam diffraction pattern at a point D shown in the cross-sectional TEM image
  • sample 1E is a point E shown in the cross-sectional TEM image.
  • the electron beam diffraction pattern of the location shown in FIG. 1 and the sample 1H obtained the electron beam diffraction pattern of the location shown at point A shown in the cross-sectional TEM image.
  • Sample 1H showed a diffraction pattern including spots presumed to originate from the crystal structure. Therefore, it can be presumed that the sample 1E has a polycrystalline region made up of microcrystals in which the grain size of one microcrystal is larger than that of the samples 1A and 1D, or the ratio of microcrystals is high. Sample 1H is considered to have a larger single crystallite grain size or a higher proportion of polycrystalline regions than sample 1E.
  • a hafnium oxide film using a sputtering method can be formed into a film having low crystallinity by using a mixed gas containing oxygen. Further, it has been found that a hafnium oxide film using a sputtering method can form a film having lower crystallinity as the deposition temperature is lower.
  • FIG. 39 shows the laminated structure of each sample.
  • Sample 2A, Sample 2B, Sample 2C, Sample 2D, Sample 2E, Sample 2F, Sample 2G, and Sample 2H are a substrate 920, an insulator 922 on the substrate 920, and an insulator 924 on the insulator 922, respectively.
  • hafnium oxide films having different film formation conditions were used as the insulator 924.
  • the following table shows the film formation temperature of the insulator 924 in Samples 2A to 2H.
  • a silicon wafer was prepared as the substrate 920.
  • a silicon oxide film with a thickness of 100 nm was formed as the insulator 922 by a thermal oxidation method over the substrate 920.
  • samples 2A to 2H were subjected to heat treatment at 600 ° C. for 1 hour in a nitrogen atmosphere.
  • a hafnium oxide film with a thickness of 5 nm was formed as the insulator 924 over the insulator 922 by using a sputtering apparatus.
  • the hafnium oxide film is formed using a hafnium oxide target in a mixed atmosphere of oxygen (O 2 ) and argon (Ar) or in an oxygen (O 2 ) atmosphere, at a pressure of 0.7 Pa, and the target and the substrate.
  • the distance between and was set to 60 mm, and 2.5 kW of power (RF) was applied to form a film.
  • the oxygen flow rate ratio of the sputtering gas and the film formation temperature were in accordance with the above table.
  • FIG. 40 shows the results of TDS analysis before and after the heat treatment for Samples 2A to 2H.
  • FIG. 40 shows the amount of released oxygen [pieces / cm 2 ] for each sample.
  • the release of oxygen was confirmed in the insulator 922 in Samples 2A to 2H before the heat treatment. That is, it was found that by forming the insulator 924, an excess oxygen region is formed in the insulator 922. In particular, it was confirmed that by depositing the insulator 924 in a mixed atmosphere containing oxygen, excess oxygen can be transferred to the insulator 922 more efficiently than in a film containing only oxygen.

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Abstract

La présente invention concerne un dispositif à semiconducteur ayant des propriétés électriques stables. La présente invention concerne également un dispositif à semiconducteur ayant une fiabilité élevée. Ce dispositif à semiconducteur comprend une électrode de grille, une électrode de source, une électrode de drain, un semiconducteur d'oxyde ayant une région de formation de canal, et un isolant de grille. L'isolant de grille comprend une première couche en contact avec la région de formation de canal et une seconde couche sur la première couche, la seconde couche étant un oxyde métallique, et l'oxyde métallique a une rugosité de surface moyenne quadratique (RMS) inférieure ou égale à 0,4 nm dans une plage de mesure de 1000 nm x 1000 nm.
PCT/IB2018/051212 2017-03-07 2018-02-27 Dispositif à semiconducteur et procédé de fabrication d'un dispositif à semiconducteur WO2018163013A1 (fr)

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JP2008243929A (ja) * 2007-03-26 2008-10-09 Idemitsu Kosan Co Ltd 半導体装置、半導体装置の製造方法及び表示装置
JP2013128106A (ja) * 2011-11-18 2013-06-27 Semiconductor Energy Lab Co Ltd 絶縁膜およびその形成方法、ならびに半導体装置およびその作製方法
JP2014179596A (ja) * 2013-02-12 2014-09-25 Semiconductor Energy Lab Co Ltd 半導体装置
JP2015032655A (ja) * 2013-08-01 2015-02-16 出光興産株式会社 薄膜トランジスタ
JP2015057819A (ja) * 2013-08-09 2015-03-26 株式会社半導体エネルギー研究所 半導体装置

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Publication number Priority date Publication date Assignee Title
JP2008243929A (ja) * 2007-03-26 2008-10-09 Idemitsu Kosan Co Ltd 半導体装置、半導体装置の製造方法及び表示装置
JP2013128106A (ja) * 2011-11-18 2013-06-27 Semiconductor Energy Lab Co Ltd 絶縁膜およびその形成方法、ならびに半導体装置およびその作製方法
JP2014179596A (ja) * 2013-02-12 2014-09-25 Semiconductor Energy Lab Co Ltd 半導体装置
JP2015032655A (ja) * 2013-08-01 2015-02-16 出光興産株式会社 薄膜トランジスタ
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