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WO2018181445A1 - Substrat à matrice active et appareil d'affichage équipé dudit substrat - Google Patents

Substrat à matrice active et appareil d'affichage équipé dudit substrat Download PDF

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Publication number
WO2018181445A1
WO2018181445A1 PCT/JP2018/012680 JP2018012680W WO2018181445A1 WO 2018181445 A1 WO2018181445 A1 WO 2018181445A1 JP 2018012680 W JP2018012680 W JP 2018012680W WO 2018181445 A1 WO2018181445 A1 WO 2018181445A1
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WIPO (PCT)
Prior art keywords
potential
pixel
gate line
gate
tft
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PCT/JP2018/012680
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English (en)
Japanese (ja)
Inventor
示寛 横野
隆之 西山
諒 米林
耕平 田中
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シャープ株式会社
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Publication of WO2018181445A1 publication Critical patent/WO2018181445A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to an active matrix substrate and a display device including the same.
  • a drive circuit for switching a gate line to a selected state is provided in a display area for each gate line.
  • the drive circuit includes a plurality of switching elements and an internal wiring to which some of the switching elements are connected, and is distributed to a plurality of pixels in the vicinity of the corresponding one gate line.
  • the active matrix substrate is provided with a control wiring for supplying a control signal to each drive circuit. In accordance with the supplied control signal, the potential of the internal wiring in the driver circuit varies, and a voltage signal for selecting or deselecting the gate line is output to the gate line.
  • the potential of the control wiring provided near the gate line may change at the timing when the gate line is switched from the selected state to the non-selected state.
  • the common electrode arranged facing the pixel electrode provided in each pixel is affected by the potential variation of the wiring.
  • the fluctuation of the potential of the control wiring propagates to the pixel electrode connected to the gate line that is switched to the non-selected state at the timing when the potential of the wiring fluctuates, resulting in uneven brightness.
  • An active matrix substrate has a display region composed of a plurality of pixels formed in a matrix by a plurality of gate lines and a plurality of source lines, the pixel electrode provided in each pixel, and the pixel electrode Each of the plurality of gate lines in the display region and corresponding to the supplied driving signal.
  • the first potential and the second potential lower than the first potential are repeated in a cycle of supplying N-phase (N: integer of 8 or more) driving signals having different phases
  • N-phase (N: integer of 8 or more) driving signals having different phases
  • some of the control wirings have a wiring portion substantially parallel to the gate line, and some of the plurality of gate lines receive a driving signal supplied to the wiring portion.
  • the wiring portion is switched to a non-selected state, and the wiring portion is at least N / N from a pixel provided with a pixel electrode connected to the part of the gate lines. Arranged in pixels that are four or more rows away.
  • the luminance unevenness of the pixels can be reduced.
  • FIG. 1 is a schematic diagram illustrating a schematic configuration of a liquid crystal display device according to an embodiment.
  • FIG. 2 is a schematic diagram showing a schematic configuration of the active matrix substrate shown in FIG.
  • FIG. 3 is a schematic diagram illustrating a schematic configuration of the pixel illustrated in FIG. 2.
  • FIG. 4 is a schematic diagram showing a schematic configuration of each part connected to the active matrix substrate and the active matrix substrate shown in FIG.
  • FIG. 5 is a timing chart showing changes in potentials of eight clock signals and gate lines in the embodiment.
  • FIG. 6 is a diagram showing an example of an equivalent circuit of the gate driver shown in FIG.
  • FIG. 7A is a schematic diagram illustrating an arrangement example of the gate driver illustrated in FIG. 4.
  • FIG. 7B is a schematic diagram illustrating an arrangement example of the gate driver illustrated in FIG. 4.
  • FIG. 8 is a timing chart showing changes in the potential of the clock signal and the gate line in the application example.
  • FIG. 9 is a schematic diagram showing a schematic configuration of an active matrix substrate and each part connected to the active matrix substrate in an application example.
  • FIG. 10A is a schematic diagram illustrating an arrangement example of the gate driver illustrated in FIG. 9.
  • FIG. 10B is a schematic diagram illustrating an arrangement example of the gate driver illustrated in FIG. 9.
  • An active matrix substrate includes a display region composed of a plurality of pixels formed in a matrix by a plurality of gate lines and a plurality of source lines, and a pixel electrode provided in each pixel;
  • An active matrix substrate including a common electrode disposed opposite to the pixel electrode, the active matrix substrate being provided corresponding to each of the plurality of gate lines in the display region, according to a drive signal supplied
  • the wiring repeats the first potential and the second potential lower than the first potential at a constant cycle, and outputs N-phase (N: integer of 8 or more) driving signals having different phases.
  • Some of the plurality of control wirings have a wiring portion substantially parallel to the gate line, and some of the plurality of gate lines are supplied to the wiring portion.
  • the pixel In a period in which the driving signal changes from the first potential to the second potential, the pixel is switched to a non-selected state, and the wiring portion is provided with a pixel electrode connected to the partial gate line Are arranged in pixels at least N / 4 rows away from the first (first configuration).
  • a drive circuit that switches a gate line to a selected or non-selected state is provided in the display area of the active matrix substrate, and a control wiring that supplies a drive signal to the drive circuit is provided.
  • the driving signal includes an N-phase signal (N: an integer of 8 or more) that repeats the first potential and the second potential at a constant period.
  • the control wiring has a wiring portion substantially parallel to the gate line.
  • the wiring portion includes at least N pixels from a pixel provided with a pixel electrode connected to a part of the gate lines that are switched to a non-selected state during a period in which the potential of the wiring portion changes to the second potential among the plurality of gate lines. / 4 or more rows, that is, provided in pixels separated by 2 rows or more.
  • the pixel electrode is opposed to a pixel in which a pixel electrode connected to a gate line that is affected by the fluctuation of the potential of the wiring portion is arranged or in a row adjacent to the pixel, compared to the case where the wiring portion is provided.
  • the distance between the common electrode arranged in this manner and the wiring portion is increased.
  • the common electrode is unlikely to be affected by fluctuations in the potential of the wiring portion, and fluctuations in the potential that the pixel electrode receives via the common electrode are reduced, so that unevenness in luminance can be reduced.
  • one drive circuit has an internal wiring that is substantially parallel to a gate line, and the potential of the internal wiring changes in substantially the same phase as the part of the control wiring, and the wiring portion is It is good also as arrange
  • the drive circuit has an internal wiring that changes in potential at substantially the same phase as a part of the control wiring and is substantially parallel to the gate line.
  • the internal wiring is arranged in the same row as a wiring portion substantially parallel to the gate line in some control wirings. Therefore, compared to the case where the internal wiring is provided in a pixel provided with a pixel electrode connected to the part of the gate lines or a pixel in an adjacent row, the potential of the internal wiring is connected to the pixel electrode of these pixels. Fluctuations are difficult to propagate. Therefore, it is possible to reduce luminance unevenness caused by fluctuations in the potential of not only the wiring portion that supplies the driving signal but also the internal wiring.
  • the N-phase driving signal repeats the first potential and the second potential every four horizontal scanning periods, and the eight phases are shifted in phase by 1 ⁇ 4 period. (The third configuration).
  • the third configuration it is possible to reduce the power consumption for supplying the driving signals as compared with the case where the driving signals are supplied in a cycle shorter than the four horizontal scanning periods.
  • the N-phase driving signal repeats the first potential and the second potential every 8 horizontal scanning periods, and is 16 phases out of phase by 1/8 period. (4th structure).
  • the distance between the common electrode disposed opposite to the pixel electrode and the control wiring that affects the potential of the pixel electrode is further increased than in the second configuration. Therefore, the fluctuation of the potential that the pixel electrode receives through the common electrode becomes smaller. As a result, luminance unevenness can be further reduced as compared with the second configuration.
  • a display device includes a first to fourth active matrix substrate, a counter substrate having a color filter, and a liquid crystal sandwiched between the active matrix substrate and the counter substrate. And a layer (fifth configuration).
  • FIG. 1 is a schematic diagram showing a schematic configuration of the liquid crystal display device according to the present embodiment.
  • the liquid crystal display device 1 includes a display panel 2, a source driver 3, a display control circuit 4, and a power source 5.
  • the display panel 2 includes an active matrix substrate 20a, a counter substrate 20b, and a liquid crystal layer (not shown) sandwiched between these substrates.
  • a pair of polarizing plates is provided so as to sandwich the active matrix substrate 20a and the counter substrate 20b.
  • a black matrix (BM) and three color filters (not shown) of red (R), green (G), and blue (B) are formed on the counter substrate 20b.
  • the active matrix substrate 20a is electrically connected to the source driver 3 formed on the flexible substrate.
  • the display control circuit 4 is electrically connected to the display panel 2, the source driver 3, and the power source 5.
  • the display control circuit 4 outputs control signals to the source driver 3 and a drive circuit (hereinafter referred to as a gate driver) provided on the active matrix substrate 20a.
  • the power supply 5 is electrically connected to the display panel 2, the source driver 3, and the display control circuit 4, and supplies a power supply voltage signal to each.
  • FIG. 2 is a schematic diagram showing a schematic configuration of the active matrix substrate 20a.
  • M M: natural number
  • gate lines 13 (1) to 13 (M) are formed substantially in parallel at regular intervals from one end to the other end in the X-axis direction.
  • gate lines 13 A plurality of source lines 15 are formed on the active matrix substrate 20 a so as to intersect with the gate lines 13.
  • a region surrounded by the gate line 13 and the source line 15 forms one pixel.
  • Each pixel PIX corresponds to one of the colors of the color filter, and is arranged in the order of R, G, B in the extending direction of the gate line 13.
  • FIG. 3 is a schematic diagram showing a schematic configuration of some pixels in the active matrix substrate 20a.
  • the pixel PIX includes a thin film transistor 10 (TFT: Thin Film Transistor) (hereinafter referred to as a pixel TFT) connected to one gate line 13 and one source line 15 constituting the pixel PIX. .
  • TFT Thin Film Transistor
  • the drain electrode of the pixel TFT 10 is connected to the pixel electrode PXB.
  • the display panel 2 in the present embodiment is, for example, an FFS (Fringe Field Switching) mode liquid crystal panel.
  • the pixel electrode PXB is made of, for example, a transparent conductive film such as ITO and has a plurality of slits.
  • the active matrix substrate 20a is provided with a common electrode made of a transparent conductive film such as ITO so as to face the pixel electrode PXB via an insulating film.
  • a data signal voltage is input to the pixel electrode PXB from the source driver 3 (see FIG. 2) via the source line 15.
  • a predetermined voltage is applied to the common electrode (not shown) by the display control circuit 4 (see FIG. 1).
  • the potential of the pixel PIX corresponds to the potential of the source line 15, the capacitance Cgd between the pixel electrode PXB and the gate line 13, and the pixel electrode PXB and a common electrode (not shown) according to the potential change of the gate line 13. And the capacitance Ccom between them.
  • FIG. 4 is a schematic diagram showing a schematic configuration of each part connected to the active matrix substrate 20a and the active matrix substrate 20a.
  • the source line 15 is not shown for convenience.
  • one gate driver 11 is connected to each gate line 13.
  • the gate driver 11 (1) connected to the gate line 13 (1)
  • the gate driver 11 (9) connected to the gate line 13 (9)
  • the gate driver connected to the gate line 13 (17) 11 (17)... are connected to each other via the control wiring 16.
  • the gate driver (2) connected to the gate line 13 (2)
  • the gate driver 11 (10) connected to the gate line 13 (10)
  • the gate driver connected to the gate line 13 (18). 11 (18)... are connected to each other via the control wiring 16. That is, in this example, each gate driver 11 is connected to another gate driver 11 connected to the eighth gate line 13 through the control wiring 16 from the gate line 13 to which the gate driver 11 is connected. .
  • the gate driver 11 (1) is arranged between the gate line 13 (3) and the gate line 13 (4), and the gate driver 11 (2) is connected to the gate line 13 (4) and the gate line. Arranged between the lines 13 (5). That is, in this example, each gate driver 11 is arranged between the gate line 13 connected to the second and third rows from the connected gate line 13.
  • one gate driver 11 is provided for one gate line 13, but a plurality of gate drivers 11 may be provided for one gate line 13.
  • terminal portions 12g and 12s are provided in the frame region on the side where the source driver 3 is provided.
  • the terminal portion 12g is connected to the display control circuit 4 and the power source 5.
  • the terminal portion 12s is connected to the display control circuit 4, the source driver 3, and the source line 15 (see FIG. 2).
  • the display control circuit 4 has, as a control signal, a signal that repeats an H level (VDD) and an L level (VSS) every 4 horizontal periods (hereinafter referred to as a clock signal), and the same potential as the H level of the clock signal.
  • a signal (hereinafter referred to as a reset signal) is supplied to the terminal portion 12g.
  • the power supply 5 supplies a power supply voltage signal to the source driver 3 and the terminal unit 12g.
  • the terminal unit 12 g receives the supplied control signal, power supply voltage signal, and the like, and supplies each signal to each gate driver 11 via the control wiring 16.
  • the gate driver 11 outputs a voltage signal indicating one of a selected state and a non-selected state to the corresponding gate line 13 in accordance with the supplied signal.
  • the state where the gate line 13 is selected is referred to as driving of the gate line 13.
  • the source driver 3 outputs a data signal to each source line 15 (see FIG. 2) via the terminal portion 12s in accordance with a signal input from the display control circuit 4.
  • FIG. 6 is a diagram illustrating an equivalent circuit of the gate driver 11 (n) connected to the gate line 13 (n).
  • n 8j + 1
  • j is an integer of 0 or more.
  • the gate driver 11 (n) includes thin film transistors (TFT: Thin Film Transistor) (hereinafter referred to as TFT-A to TFT-J) indicated by alphabets A to J and a capacitor Cbst as switching elements.
  • TFT Thin Film Transistor
  • netA the internal wiring in which the source terminal of TFT-B, the drain terminals of TFT-A and TFT-C, the gate terminal of TFT-F, and one electrode of capacitor Cbst are connected.
  • netB An internal wiring in which the source terminal of TFT-G, the drain terminals of TFT-H, TFT-I, and TFT-J and the gate terminal of TFT-C are connected is referred to as netB.
  • TFT-A The drain terminal of TFT-A is connected to netA, the reset signal CLR is supplied to the gate terminal, and the power supply voltage signal VSS is supplied to the source terminal.
  • the TFT-A lowers netA (n) to L level (VSS) in accordance with the potential of the reset signal CLR.
  • the gate terminal of TFT-B is connected to gate line 13 (n-1), and the source terminal is connected to netA (n) in gate driver 11 (n).
  • the TFT-B receives the potential of the gate line 13 (n-4) as the set signal S.
  • the TFT-B in the gate driver 11 that drives the gate line 13 (1) receives the gate start pulse signal output from the display control circuit 4 as the set signal S.
  • the gate terminal of the TFT-B in the gate driver 11 (n) is the potential of the gate line 13 (n-4) driven four horizontal scanning periods before the driving timing of the gate line 13 (n). Is entered.
  • the TFT-B outputs the potential of the set signal S to the netA (n) according to the potential of the gate line 13 (n-4), and charges (precharges) the netA (n).
  • TFT-C has a gate terminal connected to netB (n), a drain terminal connected to netA (n), and a power supply voltage signal VSS is supplied to the source terminal.
  • TFT-C sets netA (n) to L level (VSS) in accordance with the potential of netB (n).
  • the TFT-F has a gate terminal connected to netA (n), a source terminal connected to the gate line 13 (n), and a clock signal CKA supplied to the drain terminal.
  • the TFT-F outputs the potential of the clock signal CKA to the gate line 13 (n) according to the potential of netA (n), charges the capacitor Cbst, and switches the gate line 13 (n) to the selected state.
  • the capacitor Cbst has one electrode connected to the netA (n) and the other electrode connected to the gate line 13 (n).
  • the capacitor Cbst boosts the potential of netA (n) in accordance with the potential of the clock signal CKA output from the TFT-F.
  • the TFT-E has a drain terminal connected to the gate line 13 (n), a reset signal CLR supplied to the gate terminal, and a power supply voltage signal VSS supplied to the source terminal.
  • the TFT-E sets the potential of the gate line 13 (n) to L level (VSS) in accordance with the potential of the reset signal CLR.
  • the TFT-D has a drain terminal connected to the gate line 13 (n), a clock signal CKB supplied to the gate terminal, and a power supply voltage signal VSS supplied to the source terminal.
  • the TFT-D sets the potential of the gate line 13 (n) to L level (VSS) in accordance with the potential of the clock signal CKB.
  • a gate terminal and a drain terminal are connected, a clock signal CKB is supplied to the gate terminal and the drain terminal, and a source terminal is connected to netB (n).
  • the TFT-G outputs a potential of (H level potential of the clock signal CKB ⁇ threshold voltage) to the netB (n) in accordance with the potential of the clock signal CKB.
  • TFT-H has a drain terminal connected to netB (n), a gate terminal supplied with a clock signal CKA, and a source terminal supplied with a power supply voltage signal VSS.
  • the TFT-H sets the potential of netB (n) to L level (VSS) in accordance with the potential of the clock signal CKA.
  • TFT-I has a drain terminal connected to netB (n), a gate terminal supplied with a reset signal CLR, and a source terminal supplied with a power supply voltage signal VSS.
  • the TFT-I sets the potential of netB (n) to L level (VSS) in accordance with the potential of the reset signal CLR.
  • the drain terminal is connected to netB (n)
  • the gate terminal is connected to the gate line 13 (n-4)
  • the power supply voltage signal VSS is supplied to the source terminal.
  • the TFT-J receives the potential of the gate line 13 (n-4) as the set signal S.
  • the TFT-J in the drive circuit 11 that drives the gate line 13 (1) receives the gate start pulse signal output from the display control circuit 4 as the set signal S.
  • the TFT-J sets the potential of netB (n) to L level (VSS) according to the potential of the set signal S.
  • FIG. 5 is a timing chart showing changes in the potentials of the eight clock signals and changes in the potentials of the gate lines 13 (n) and 13 (n ⁇ 1) and netA (n) and netB (n) in this embodiment. It is.
  • the phase is shifted by a quarter cycle, and an 8-phase clock signal that alternately repeats an H level (VDD) potential and an L level (VSS) potential every four horizontal scanning periods (4H).
  • VDD H level
  • VSS L level
  • CK1A to CK4A and CK1B to CK4B are used.
  • the reset signal CLR is not shown, but the reset signal CLR is a signal that is at the H level for each vertical scanning period and is output from the display control circuit 4 for each frame.
  • the clock signals CKA and CKB supplied to the TFT-F and TFT-H and the TFT-D and TFT-G of the gate driver 11 are the clock signals CK1A to CK4A and CK1B to CK4B, respectively.
  • the combinations of the clock signals CKA and CKB are (CK1A, CK1B), (CK2A, CK2B), (CK3A, CK3B), (CK4A, CK4B), (CK1B, CK1A), (CK2B, CK2A), (CK3B, CK3A) , (CK4B, CK4A).
  • Each gate driver 11 is supplied with a clock signal that is shifted from the clock signal supplied to the gate driver 11 that drives the previous gate line 13 by a quarter of a cycle. That is, when the combination of the clock signals CKA and CKB supplied to the gate driver 11 (n) is (CK1A, CK1B), the combination of the clock signals CKA and CKB supplied to the gate driver 11 (n + 1) is (CK2A , CK2B), and the combination of the clock signals CKA and CKB supplied to the gate driver 11 (n-1) is (CK4B, CK4A).
  • the gate driver 11 (n) is supplied with the clock signal CK1A as the clock signal CKA and the clock signal CK1B as the clock signal CKB.
  • the H level potential of the gate line 13 (n-4) is input to the TFT-B, J, and the TFT-B, J is turned on.
  • TFT-B When TFT-B is turned on, a potential (VDD-Vth (B)) that is smaller than the H-level potential by the threshold voltage (Vth (B)) of TFT-B is precharged to netA (n). .
  • the clock signal CK1A having the L level potential is supplied to the drain terminal of the TFT-F, and the clock signal CK1B having the H level potential is supplied to the gate terminals of the TFT-D and G.
  • the TFT-D, G, and F are turned on, and the gate line 13 (n) maintains the L level potential (VSS).
  • netB (n) divided the H level potential input to TFT-G and the L level potential input to TFT-J. Charged to potential.
  • TFT-J is designed to be larger than TFT-G, and netB (n) is charged to a potential close to the L level input to TFT-J.
  • the clock signal CK1A maintains the L level potential
  • the clock signal CK1B maintains the H level potential. Therefore, between time t5 and t9, netA (n) maintains a precharged state, and gate line 13 (n) maintains a non-selected state. Further, the gate line 13 (n-4) maintains a selected state from time t5 to t9, becomes an L level potential at time t9, and is switched to a non-selected state. Therefore, TFT-B and J are turned on from time t5 to t9, and are turned off after time t9. Therefore, since the TFT-J and the TFT-G are simultaneously turned on from the time t5 to the time t9, the netB (n) maintains a potential close to the L level.
  • the potential of the clock signal CK1A transitions to the H level, and the potential of the clock signal CK1B transitions to the L level.
  • the potential of netA (n) is pushed up to a potential higher than the H level by the capacitor Cbst.
  • the potential of the clock signal CK1B is at the L level, and the TFTs D and G are turned off. Therefore, the potential of the gate line 13 (n) is changed from the L level to the H level and switched to the selected state.
  • netB (n) changes to H level or L level at the timing of turning on / off TFT-G. That is, after time t9, netB (n) is charged to H level or L level according to the potential of the clock signal CK1B.
  • the clock signal CK1A maintains the H level potential
  • the clock signal CK1B maintains the L level potential. Therefore, the state in which the gate line 13 (n) is selected is maintained from time t9 to t10, and netB (n) maintains the L level potential.
  • the potential of the clock signal CK1A changes from the H level to the L level
  • the potential of the clock signal CK1B changes from the L level to the H level.
  • TFT-D and G are turned on, and TFT-H is turned off.
  • an L level (VSS) potential is input to the gate line 13 (n), and the gate line 13 (n) is switched to a non-selected state.
  • netB (n) is supplied with an H level potential via the TFT-G, and the TFT-C is turned on. Therefore, netA (n) receives an L-level (VSS) potential via TFT-C and maintains the L-level potential after time t10.
  • the display control circuit 4 supplies a data signal to be written to the pixel in which the pixel TFT 10 connected to the gate line 13 (n) is arranged between the time t9 and t10 to the source line 15 through the terminal portion 12s. To do. Thereby, in one frame period, after time t10 when the gate line 13 (n) is in a non-selected state, a voltage corresponding to the data signal via the pixel TFT 10 is held by the pixel electrode PXB in the pixel.
  • the gate line 13 (n) is switched to the non-selected state, and the clock signal CK1B changes from H level to L level.
  • the gate line 13 (n + 4) is switched to the non-selected state at the timing (t11) when it changes to.
  • the common electrode (not shown) provided in the pixel is the gate line 13.
  • the potential of (n) changes from the H level to the L level, it is influenced by the fluctuation of the potential of the control wiring 16, and becomes a potential smaller than the original potential.
  • a common electrode (not shown) provided in the pixel is At the timing when the potential of the gate line 13 (n + 4) changes from the H level to the L level, it is affected by the fluctuation of the potential of the control wiring 16, and becomes a potential lower than the original potential. As a result, the potential of the pixel electrode connected to the gate line 13 (n) and the gate line 13 (n + 4) is also lower than the potential to be originally held through the common electrode. 15 and the pixel TFT 10 are connected, so that the potential is slightly recovered to the original level.
  • each gate driver 11 is provided with a pixel electrode connected to the gate line 13 that is switched to a non-selected state at the timing when the potential of the clock signal supplied to the gate driver 11 changes to L level.
  • the pixel is arranged at least two rows away from the selected pixel.
  • FIGS. 7A and 7B are schematic views showing an arrangement example of the gate driver 11 (n) in the present embodiment.
  • TFT-A to TFT-J in the gate driver 11 (n) are represented by only alphabets A to J, omitting the notation “TFT-” in FIGS. 7A and 7B.
  • 7A and 7B are continuous in the column 201.
  • the gate driver 11 (n) is a black matrix (not shown) provided on the counter substrate 20b (see FIG. 1) in the row Pn + 2 of the pixel PIX provided with the pixel electrode PXB connected to the gate line 13 (n + 2). ) Is provided in the light shielding area covered by the
  • the control wiring 16 for supplying the clock signal CKA (CK1A) to the gate terminal of the TFT-H of the gate driver 11 (n) is connected to the gate line 13 (n + 2) from the terminal portion 12g (see FIG. 4).
  • the pixel electrode PXB is provided so as to extend substantially parallel to the source line 15 to the pixel row Pn + 2 and is arranged to be substantially parallel to the gate line 13 in the row Pn + 2 up to the pixel provided with the TFT-H. Yes. Further, as shown in FIG.
  • the control wiring 16 for supplying the clock signal CKB (CK1B) to the gate terminal of the TFT-D of the gate driver 11 (n) extends substantially parallel to the source line 15 up to the row Pn + 2,
  • the gate line 13 is disposed substantially parallel to the gate terminal of the TFT-D.
  • a portion 161 (hereinafter referred to as a partial wiring 161) of the control wiring 16 that supplies the clock signals CK1A and CK1B and is substantially parallel to the gate line 13 is provided in the light shielding region of the pixel in the row Pn + 2.
  • the gate line 13 (n-4) is also switched to the non-selected state at the timing when the potential of the clock signal CK1B changes to the L level, like the gate line 13 (n + 4).
  • the partial wiring 161 for supplying the clock signal CK1B to the gate driver 11 (n) is the sixth pixel (row Pn + 2) from the pixel provided with the pixel electrode connected to the gate line 13 (n-4). ).
  • the common electrode (not shown) in the row Pn + 2 is affected by fluctuations in the potential of the control wiring 16 that supplies the clock signals CK1A and CK1B, but the common electrode (not shown) in rows other than the row Pn + 2 is also common in the row Pn + 2.
  • the electrodes are affected by fluctuations in the potential of the control wiring 16 that supplies the clock signals CK1A and CK1B via the electrodes.
  • the common electrode in a row other than the row Pn + 2 has less potential variation than the common electrode in the row Pn + 2.
  • the magnitude of the variation in the potential of the common electrode in each row is ⁇ Vcom (N + 2)> ⁇ Vcom (n + 1)> ⁇ Vcom (n).
  • the potential of the pixel electrode provided in the pixel in each row varies under the influence of the variation in the potential of the common electrode in the pixel provided with the pixel electrode.
  • the gate driver 11 (n) is connected to a gate line 13 (13 (n), (n + 8), (n-4), (n + 4)) that is affected by the potential of the clock signal supplied to the gate driver 11.
  • the pixel electrode is disposed at a distance of at least two rows from the pixel provided with the pixel electrode. Further, the partial wiring 161 that affects the potential of the pixel electrode is also disposed in a pixel that is separated from the pixel provided with the pixel electrode by at least two rows. Therefore, the gate driver 11 is provided with the pixel electrode as compared with the case where the gate driver 11 is arranged in the row of the pixel provided with the pixel electrode affected by the potential of the clock signal supplied to the gate driver 11 or in the adjacent row. The distance between the common electrode of the selected pixel and the partial wiring 161 that supplies the clock signal is increased. As a result, the pixel electrode is not easily affected by fluctuations in the potential of the control wiring 16 via the common electrode, and luminance unevenness can be reduced.
  • the partial wiring 161 connected to the gate driver 11 but also the internal wirings netA and netB in the gate driver 11 are provided with pixel electrodes that are affected by the potential of the clock signal supplied to the gate driver 11. Are arranged in pixels that are two or more rows away from each other.
  • the potential of the internal wiring netA (n) in the gate driver 11 (n) becomes L level at the timing when the gate line 13 (n) switches to the non-selected state.
  • the potential of the internal wiring netB (n) in the gate driver 11 (n) changes at the same phase as the clock signal CK1B, and the potential becomes L level at the timing when the gate line 13 (n + 4) switches to the non-selected state.
  • the internal wirings netA (n) and netB (n) are also arranged two or more rows away from the pixel provided with the pixel electrode connected to these gate lines, so that these pixel electrodes are connected to the potential of the internal wiring. Can be made less susceptible to fluctuations.
  • FIG. 8 is a timing chart showing a change in the potential of the clock signal and a change in the potential of the gate line 13 in this application example.
  • the 16-phase clock signals CK1A to CK8A and CK1B to CK8B in this application example are shifted in phase by 1/8 period, and at the H level and the L level every 8 horizontal scanning periods (8H). Repeat the potential alternately.
  • the reset signal CLR is not shown, the reset signal CLR is a signal that is at the H level for a certain period every vertical scanning period, as in the above-described embodiment, and every frame. Output from the display control circuit 4.
  • the clock signals CKA and CKB supplied to the gate driver 11 are two clock signals having opposite phases, and the combination of the clock signals CKA and CKB in this embodiment is (CK1A, CK1B), (CK2A, CK2B). , (CK3A, CK3B), (CK4A, CK4B), (CK5A, CK5B), (CK6A, CK6B), (CK7A, CK7B), (CK8A, CK8B), (CK1B, CK1A), (CK2B, CK2A), ( CK3B, CK3A), (CK4B, CK4A), (CK5B, CK5A), (CK6B, CK6A), (CK7B, CK7A), (CK8B, CK8A).
  • the configuration of the gate driver 11 in this application example is the same as the configuration shown in FIG. 6, but is different from the above embodiment in the following points.
  • n 16j + 1 (j is an integer equal to or larger than 0)
  • the gate line 13 (n-8) is connected to the gate terminals of the TFT-B and J of the gate driver 11 (n). ) Is supplied.
  • the combination of the clock signals CKA and CKB supplied to the gate driver 11 (n) is (CK1A, CK1B).
  • the TFTs B and J of the gate driver 11 (n) are turned on from time t9 to t10 when the potential of the gate line 13 (n-8) becomes H level, and netA (n) becomes TFT- A potential (VDD ⁇ Vth (B)) that is smaller by the threshold voltage (Vth (B)) of B is precharged to netA (n).
  • the potential of the clock signal CK1A is at the L level
  • the potential of the clock signal CK1B is at the H level
  • the TFT-D, G, and F are turned on, so that the gate line 13 (n) is at the L level potential (VSS).
  • TFT-J and TFT-G are simultaneously turned on, and netB (n) is charged to a potential close to the L level input to TFT-J.
  • the potential of the clock signal CK1A transitions to the H level, and the potential of the clock signal CK1B transitions to the L level.
  • the potential of netA (n) is pushed up to a potential higher than the H level by the capacitor Cbst.
  • the potential of the clock signal CK1B is at the L level, and the TFTs D and G are turned off. Therefore, the potential of the gate line 13 (n) is changed from the L level to the H level and switched to the selected state.
  • the clock signal CK1A maintains an H level potential and the clock signal CK1B maintains an L level potential. Therefore, the gate line 13 (n) is maintained in a selected state during this period. .
  • the potential of the clock signal CK1A transitions from the H level to the L level, and the potential of the clock signal CK1B transitions from the L level to the H level, so that the TFT-D and G are turned on and the TFT-H is turned off.
  • an L level (VSS) potential is input to the gate line 13 (n), and the gate line 13 (n) is switched to a non-selected state.
  • netB (n) is the clock signal CK1B input to the TFT-G after time t10. In response to this, it is charged to a potential of H level or L level.
  • the netA (n) has the L-level (VSS) potential through the TFT-C. Input, and maintains the L level potential after time t11.
  • the gate lines 13 (n) and 13 (n + 16) are switched to the non-selected state at the timing when the potential of the clock signal CK1A changes from the H level to the L level. Further, at the timing when the clock signal CK1B changes from the H level to the L level, the gate lines 13 (n ⁇ 8) and 13 (n + 8) are switched to the non-selected state.
  • FIG. 9 is a schematic diagram showing an arrangement example of the gate driver 11 in this application example.
  • the source line 15 is not shown.
  • the gate driver 11 (1) and the gate driver 11 (17) are connected to each other via the control wiring 16.
  • the gate driver (2) and the gate driver 11 (18) are connected to each other via the control wiring 16. That is, each gate driver 11 is connected to the other gate driver 11 connected to the 16th gate line 13 through the control wiring 16 from the gate line 13 to which the gate driver 11 is connected.
  • Each gate driver 11 is disposed between the gate lines 11 in the fourth and fifth rows from the connected gate lines 11.
  • a specific example of the arrangement of the gate driver 11 will be described.
  • FIGS. 10A and 10B are schematic diagrams illustrating an arrangement example of elements of the gate driver 11 (n) in this application example.
  • TFT-A to TFT-J in the gate driver 11 (n) are represented by only alphabets A to J, omitting the notation of “TFT-” in FIGS. 10A and 10B.
  • FIGS. 10A and 10B are continuous in column 202.
  • the gate driver 11 (n) is covered with a black matrix (not shown) provided on the counter substrate 20b (see FIG. 1) in the pixel row Pn + 4 provided with the pixel electrode connected to the gate line 13 (n + 4). It is provided in the broken light shielding area.
  • the control wiring 16 for supplying the clock signal CK1A to the gate terminal of the TFT-H of the gate driver 11 (n) is connected to the gate line 13 (n + 4) from the terminal portion 12g (see FIG. 4).
  • the pixel is provided so as to extend substantially parallel to the source line 15 to the row Pn + 4 of the pixel provided with the electrode, and in the row Pn + 4, the pixel provided with the TFT-H is arranged so as to be substantially parallel to the gate line 13.
  • the control wiring 16 for supplying the clock signal CK1B to the gate terminal of the TFT-D of the gate driver 11 (n) extends substantially parallel to the source line 15 up to the row Pn + 4.
  • the gate line 13 is disposed substantially parallel to the gate terminal.
  • the partial wiring 161 that supplies the clock signals CK1A and CK1B and is substantially parallel to the gate line 13 is provided in the light shielding region of the pixel in the row Pn + 4.
  • the gate driver 11 (n) is connected to a gate line 13 (13 (n), (n + 16), (n-8), (n + 8)) that is affected by the potential of the clock signal supplied to the gate driver 11.
  • the pixel electrode is disposed at a distance of at least four rows from the pixel provided with the pixel electrode.
  • the partial wiring 161 that affects the potential of the pixel electrode is also arranged in a pixel that is separated from the pixel provided with the pixel electrode by at least four rows. Therefore, the distance between the common electrode of the pixel in which the pixel electrode is arranged and the partial wiring 161 is longer than in the above embodiment, and the potential variation through the common electrode input to the pixel electrode is reduced. Further, luminance unevenness can be reduced.
  • the pixel electrode connected to the gate line 13 that is switched to the non-selected state is provided at the timing when the two clock signals CKA and CKB supplied to the gate driver 11 change to the L level potential.
  • the gate driver 11 is disposed in a pixel that is at least two rows away from the pixel.
  • the pixel electrode connected to the gate line 13 that is switched to the non-selected state is provided at the timing when the two clock signals CKA and CKB supplied to the gate driver 11 change to the L level potential.
  • the gate driver 11 is arranged in a pixel that is at least four rows away from the pixel.
  • the gate driver 11 has the potential of the clock signal supplied to the gate driver 11 being L.
  • the pixel is arranged at least N / 4 rows or more away from the pixel provided with the pixel electrode connected to the gate line 13 that is switched to the non-selected state at the timing of changing to the level.
  • the internal wirings netA and netB in the gate driver 11 are also pixels separated by four or more rows from the pixel provided with the pixel electrode affected by the potential of the clock signal supplied to the gate driver 11. Placed in.
  • the potential of the internal wiring netA (n) in the gate driver 11 (n) becomes L level at the timing when the gate line 13 (n) switches to the non-selected state.
  • the potential of the internal wiring netB (n) in the gate driver 11 (n) changes at the same phase as the clock signal CK1B, and the potential becomes L level when the gate line 13 (n + 8) is switched to the non-selected state.
  • the internal wirings netA (n) and netB (n) are also arranged at least four rows away from the pixels provided with the pixel electrodes connected to these gate lines, so that these pixel electrodes are connected to the potentials of the internal wirings. Can be made less susceptible to fluctuations.
  • each gate driver 11 is driven using an 8-phase clock signal and an application example using a 16-phase clock signal has been described. You may let them. In short, each gate driver 11 may be driven using a clock signal of eight phases or more.
  • the pixel electrode connected to the gate line 13 that switches to the non-selected state is arranged in a pixel that is two or more rows away from the specific pixel provided with the pixel electrode, but at least the partial wiring 161 may be arranged in a pixel that is two or more rows away. Good. That is, the switching element, the capacitor, and the internal wiring configuring the gate driver 11 may be provided in the specific pixel.
  • the internal wiring is provided in the specific pixel.
  • the pixel electrode in a specific pixel is more susceptible to fluctuations in the potential of the internal wiring.
  • the influence of the potential variation received by the pixel electrode of the specific pixel is reduced. Therefore, it is desirable that both the partial wiring 161 and the internal wiring are provided in a pixel that is two or more rows away from a specific pixel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
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Abstract

L'invention concerne une technique permettant d'atténuer l'irrégularité de luminosité d'un pixel. Ce substrat de matrice active (20a) comprend une pluralité de circuits d'attaque (11), correspondant respectivement aux lignes de grille (13), qui sont prévus dans une zone d'affichage et qui commutent une ligne parmi les lignes de grille correspondantes (13) dans un état sélectionné ou non sélectionné en fonction d'un signal de commande fourni. Les circuits d'attaque (11) sont connectés dans la zone d'affichage à des fils de commande (16) qui fournissent des signaux de commande. Les signaux de commande comprennent des signaux à N phases (N étant un entier supérieur ou égal à 8) qui possèdent des phases différentes et dans lesquels un premier potentiel électrique et un second potentiel électrique inférieur au premier potentiel électrique sont répétés à des intervalles constants. Certains fils de commande (16) de la pluralité de fils de commande comprennent une partie de câblage qui est approximativement parallèle aux lignes de grille. Certaines lignes de grille (13) de la pluralité de lignes de grille (13) sont commutées dans un état non sélectionné au cours d'une période dans laquelle un potentiel électrique du signal de commande fourni à la partie de câblage évolue en second potentiel électrique. La partie de câblage est disposée dans un pixel espacé d'au moins N/4 lignes d'un pixel dans lequel est prévue une électrode de pixel connectée à certaines lignes de grille (13).
PCT/JP2018/012680 2017-03-31 2018-03-28 Substrat à matrice active et appareil d'affichage équipé dudit substrat WO2018181445A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11184406A (ja) * 1997-12-24 1999-07-09 Sony Corp 液晶ディスプレイ装置
WO2012157545A1 (fr) * 2011-05-18 2012-11-22 シャープ株式会社 Circuit de pilotage pour ligne de signaux de balayage, dispositif d'affichage muni de ce circuit et procédé de pilotage pour ligne de signaux de balayage
WO2016080498A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Substrat de matrice active et panneau d'affichage
WO2016080500A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Substrat de matrice active, et dispositif d'affichage équipé dudit substrat

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11184406A (ja) * 1997-12-24 1999-07-09 Sony Corp 液晶ディスプレイ装置
WO2012157545A1 (fr) * 2011-05-18 2012-11-22 シャープ株式会社 Circuit de pilotage pour ligne de signaux de balayage, dispositif d'affichage muni de ce circuit et procédé de pilotage pour ligne de signaux de balayage
WO2016080498A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Substrat de matrice active et panneau d'affichage
WO2016080500A1 (fr) * 2014-11-21 2016-05-26 シャープ株式会社 Substrat de matrice active, et dispositif d'affichage équipé dudit substrat

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