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WO2018122949A1 - Inductor element - Google Patents

Inductor element Download PDF

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Publication number
WO2018122949A1
WO2018122949A1 PCT/JP2016/088860 JP2016088860W WO2018122949A1 WO 2018122949 A1 WO2018122949 A1 WO 2018122949A1 JP 2016088860 W JP2016088860 W JP 2016088860W WO 2018122949 A1 WO2018122949 A1 WO 2018122949A1
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Prior art keywords
inductor
shield
semiconductor substrate
inductor element
wiring layer
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PCT/JP2016/088860
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French (fr)
Japanese (ja)
Inventor
萩原　達也
孝信 藤原
下沢　充弘
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三菱電機株式会社
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Priority to PCT/JP2016/088860 priority Critical patent/WO2018122949A1/en
Publication of WO2018122949A1 publication Critical patent/WO2018122949A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to an inductor element disposed on a semiconductor substrate on which a high-frequency circuit is integrated.
  • inductor elements are used in high-frequency circuits.
  • a spiral-shaped inductor is disposed on a conductive silicon substrate, high-frequency current leaks to the silicon substrate through a parasitic capacitance between the inductor and the silicon substrate, and loss occurs due to the resistance component of the silicon substrate. to degrade.
  • a conductive shield is disposed between the spiral-shaped inductor and the silicon substrate. This shield suppresses leakage of high-frequency current to the silicon substrate through the parasitic capacitance, so that deterioration of the Q value of the inductor is reduced.
  • an eddy current having a large diameter flows in the winding direction due to the magnetic field generated in the inductor through the conductive shield.
  • the generation of a large eddy current is suppressed by providing a plurality of slits in a direction orthogonal to the inductor wiring.
  • Non-Patent Document 1 a shield is formed on the entire surface between the inductor and the silicon substrate. For this reason, the magnetic field generated in the inductor penetrates the shield around it, and an eddy current having a small diameter flows through the shield. This eddy current has a problem that the Q value of the inductor deteriorates.
  • the present invention solves the above-described problems, and an object of the present invention is to obtain an inductor element that can suppress the generation of eddy current in a shield and reduce the deterioration of the Q value of the inductor.
  • An inductor element includes a semiconductor substrate, an inductor, and a shield.
  • the inductor is composed of a spiral wiring layer disposed on a semiconductor substrate.
  • the shield is made of a conductor layer having the same spiral shape as the wiring layer of the inductor, and is disposed along the inductor between the portion immediately below the inductor and the semiconductor substrate.
  • the shield made of the spiral conductor layer is provided along the inductor between the semiconductor substrate and the portion directly below the inductor, the leakage of the high-frequency current to the semiconductor substrate is suppressed, and the diameter of the shield is reduced. Generation of small eddy currents is suppressed. Thereby, it is possible to realize an inductor element in which the deterioration of the Q value of the inductor due to the eddy current of the shield is reduced.
  • FIG. 6 is a top view showing another configuration of the inductor element according to the first embodiment. It is a top view which shows the structure of the inductor element which concerns on Embodiment 2 of this invention. It is a top view which shows the structure of the inductor element which concerns on Embodiment 3 of this invention.
  • FIG. 1 is a top view showing a configuration of an inductor element 1 according to Embodiment 1 of the present invention.
  • the inductor element 1 includes a semiconductor substrate 2, an inductor 3 and a shield 4.
  • the semiconductor substrate 2 is, for example, a silicon substrate, and the inductor 3 and the shield 4 are disposed on at least one surface.
  • the inductor 3 is an inductor made of a spiral wiring layer.
  • the inductor 3 may have a square shape, a regular octagonal shape, or a circular shape as long as it has a spiral shape.
  • the shield 4 is made of the same spiral conductor layer as the inductor 3, and is provided along the inductor 3 immediately below the inductor 3 and the semiconductor substrate 2. In FIG. 1, the shield 4 is shown slightly shifted to indicate that the shield 4 is directly below the inductor 3.
  • the shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same conductor layer.
  • the spiral conductor layer is formed of a conductor having a sufficiently low sheet resistance and is connected to the ground.
  • the leakage of high-frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 is suppressed by the shield 4. Thereby, the loss resulting from the resistance component of the semiconductor substrate 2 is reduced, and deterioration of the Q value of the inductor 3 can be reduced.
  • FIG. 2 is a diagram showing an eddy current generated in the shield of the inductor element 1.
  • an eddy current having a small diameter is generated in the shield 5 around the inductor 3 due to the normal component of the magnetic field generated in the inductor 3.
  • the shield 4 is disposed directly below the shield 4 along the wiring layer of the inductor 3, the generation of eddy currents due to the normal component of the magnetic field generated in the inductor 3 is reduced. Thereby, the loss by the eddy current generated in the shield 4 can be reduced.
  • the shield 4 may have a larger wiring width than the inductor 3.
  • the shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same layer of the semiconductor substrate 2. For this reason, the inductor 3 and the shield 4 are not magnetically coupled, and an eddy current having a large diameter is not generated in the shield 4.
  • FIG. 3 is a top view showing an inductor element 1A having another configuration in the first embodiment.
  • the shield 4 is connected to the wiring layer 4 ⁇ / b> A that is disposed around the inductor 3 and has a ground potential.
  • the wiring layer 4A is desirably disposed at a position sufficiently separated from the inductor 3, for example, disposed at a position separated by at least three times the wiring width of the inductor 3. Even if comprised in this way, the effect similar to the above can be acquired.
  • the inductor element 1 includes the semiconductor substrate 2, the inductor 3, and the shield 4.
  • the inductor 3 is composed of a spiral wiring layer disposed on the semiconductor substrate 2.
  • the shield 4 is made of the same spiral conductor layer as the wiring layer of the inductor 3, and is disposed along the inductor 3 between the semiconductor substrate 2 and the portion immediately below the inductor 3.
  • the shield 4 of the inductor element 1 according to the first embodiment has a wiring width larger than that of the inductor 3. With this configuration, it is possible to further suppress the leakage current to the semiconductor substrate 2 as compared with the case where the inductor 3 and the shield 4 have the same width, and the loss due to the leakage current can also be reduced.
  • the shield 4 is grounded as shown in FIG. Thereby, the leakage of the high frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 can be suppressed.
  • FIG. FIG. 4 is a top view showing the configuration of the inductor element 1B according to the second embodiment of the present invention.
  • the inductor element 1 ⁇ / b> B includes a semiconductor substrate 2, an inductor 3, a shield 4, a wiring layer 4 ⁇ / b> A, and a plurality of slits 6.
  • Each of the plurality of slits 6 is a slit in a direction orthogonal to the signal path of the inductor 3 and is provided in the shield 4.
  • the slit 6 in the direction orthogonal to the signal path of the inductor 3 is provided in the shield 4, it is possible to suppress a large-diameter eddy current generated in the shield 4 due to magnetic coupling with the inductor 3 than the configuration shown in FIG. 3. it can. Thereby, it is possible to reduce deterioration of the Q value of the inductor 3.
  • the shield 4 may have a larger wiring width than the inductor 3 as in the first embodiment.
  • the shield 4 has the plurality of slits 6 in the direction orthogonal to the signal path of the inductor 3. With this configuration, an eddy current having a large diameter generated in the shield 4 can be suppressed, and an inductor element 1B having a small Q value deterioration can be realized.
  • FIG. 5 is a top view showing a configuration of an inductor element 1C according to the third embodiment of the present invention.
  • the inductor element 1C includes a semiconductor substrate 2, an inductor 3A, a wiring layer 4A, a shield 4B, and a ground line 7.
  • the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected. This differential inductor is used in a differential circuit.
  • one signal is differentially input to the outer wiring layer of the spiral shape and the inner wiring layer of the spiral shape, so that the virtual connection between the outer wiring layer and the inner wiring layer is virtually performed. It becomes a point.
  • the shield 4B is made of the same spiral conductor layer as that of the inductor 3A, and is disposed along the inductor 3A between the semiconductor substrate 2 and immediately below the inductor 3A.
  • the ground line 7 is disposed between the outer wiring layer and the inner wiring layer in the inductor 3A, and connects the virtual ground point of the inductor 3A and the wiring layer 4A having the ground potential.
  • the ground line 7 is also connected to the shield 4B.
  • a plurality of slits 6 in a direction orthogonal to the wiring of the inductor 3A may be provided in the shield 4B. Further, the shield 4B may have a larger wiring width than the inductor 3A, as in the first embodiment.
  • the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected.
  • a shield 4B made of a spiral conductor layer along the inductor 3A is disposed between the semiconductor substrate 2 and the part directly under the inductor 3A.
  • Inductor 3A has a virtual ground point connected to shield 4B. Similar to the first embodiment, since the shield 4B is disposed between the semiconductor substrate 2 and the inductor 3A, the leakage current to the semiconductor substrate 2 can be suppressed.
  • the shield 4B is disposed immediately below the wiring of the inductor 3A, the magnetic field generated by the inductor 3A does not penetrate the shield 4B, and the generation of a small eddy current in the shield 4B is also suppressed. As a result, it is possible to realize an inductor element 1C in which loss due to eddy current is reduced and Q value is less deteriorated.
  • the inductor element according to the present invention is suitable for a high-frequency circuit because the deterioration of the Q value is small.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An inductor element (1) is provided with a semiconductor substrate (2), an inductor (3) composed of a wire layer in a spiral shape and disposed on the semiconductor substrate (2), and a shield (4) composed of a conductive layer in the same spiral shape as the wire layer of the inductor (3) and disposed along the inductor (3) between a region immediately below the inductor (3) and the semiconductor substrate (2).

Description

インダクタ素子Inductor element

　この発明は、高周波回路が集積された半導体基板上に配置されるインダクタ素子に関する。 The present invention relates to an inductor element disposed on a semiconductor substrate on which a high-frequency circuit is integrated.

　従来から、高周波回路にインダクタ素子が使用されている。導電性のシリコン基板上にスパイラル形状のインダクタを配置すると、インダクタとシリコン基板との間の寄生容量を通して高周波電流がシリコン基板に漏れ、シリコン基板の抵抗成分によって損失が発生し、インダクタのＱ値が劣化する。 Conventionally, inductor elements are used in high-frequency circuits. When a spiral-shaped inductor is disposed on a conductive silicon substrate, high-frequency current leaks to the silicon substrate through a parasitic capacitance between the inductor and the silicon substrate, and loss occurs due to the resistance component of the silicon substrate. to degrade.

　そこで、非特許文献１に記載されるインダクタ素子では、スパイラル形状のインダクタとシリコン基板との間に導電性のシールドを配置している。このシールドによって、寄生容量を通したシリコン基板への高周波電流の漏れが抑制されるので、インダクタのＱ値の劣化が低減される。 Therefore, in the inductor element described in Non-Patent Document 1, a conductive shield is disposed between the spiral-shaped inductor and the silicon substrate. This shield suppresses leakage of high-frequency current to the silicon substrate through the parasitic capacitance, so that deterioration of the Q value of the inductor is reduced.

　ただし、導電性のシールドには、インダクタに発生した磁界によって巻線方向に径の大きい渦電流が流れる。非特許文献１に記載されるインダクタ素子では、インダクタの配線と直交する方向の複数のスリットをシールドに設けることにより、大きな渦電流の発生を抑制している。 However, an eddy current having a large diameter flows in the winding direction due to the magnetic field generated in the inductor through the conductive shield. In the inductor element described in Non-Patent Document 1, the generation of a large eddy current is suppressed by providing a plurality of slits in a direction orthogonal to the inductor wiring.

Ｃ．　Ｐａｔｒｉｃｋ　Ｙｕｅ，　ｅｔ．　ａｌ．　“　Ｏｎ－ｃｈｉｐ　ｓｐｉｒａｌ　ｉｎｄｕｃｔｏｒｓ　ｗｉｔｈ　ｐａｔｔｅｒｎｅｄ　ｇｒｏｕｎｄ　ｓｈｉｅｌｄｓ　ｆｏｒ　Ｓｉ－ｂａｓｅｄ　ＲＦ　ＩＣｓ　”　ＩＥＥＥ　ＪＯＵＲＮＡＬ　ＯＦ　ＳＯＬＩＤ－ＳＴＡＴＥ　ＣＩＲＣＵＩＴＳ，　ＶＯＬ．　３３，　ＮＯ．　５，　ＭＡＹ　１９９８．C. Patrick Yue, et. Al. “On-chip spiral inductors with patterned grounds shields for Si-based RF ICs” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998.

　しかしながら、非特許文献１に記載された従来のインダクタ素子では、インダクタとシリコン基板との間の全面にシールドが形成されている。このため、インダクタに発生した磁界が周辺にあるシールドを貫通して、シールドに径の小さい渦電流が流れる。この渦電流によってインダクタのＱ値が劣化するという課題があった。 However, in the conventional inductor element described in Non-Patent Document 1, a shield is formed on the entire surface between the inductor and the silicon substrate. For this reason, the magnetic field generated in the inductor penetrates the shield around it, and an eddy current having a small diameter flows through the shield. This eddy current has a problem that the Q value of the inductor deteriorates.

　この発明は上記課題を解決するもので、シールドの渦電流の発生を抑制してインダクタのＱ値の劣化を低減することができるインダクタ素子を得ることを目的とする。 SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to obtain an inductor element that can suppress the generation of eddy current in a shield and reduce the deterioration of the Q value of the inductor.

　この発明に係るインダクタ素子は、半導体基板、インダクタおよびシールドを備える。
　インダクタは、半導体基板上に配置されたスパイラル形状の配線層からなる。シールドは、インダクタの配線層と同じスパイラル形状の導電体層からなり、インダクタの直下と半導体基板との間にインダクタに沿って配置される。 An inductor element according to the present invention includes a semiconductor substrate, an inductor, and a shield.
The inductor is composed of a spiral wiring layer disposed on a semiconductor substrate. The shield is made of a conductor layer having the same spiral shape as the wiring layer of the inductor, and is disposed along the inductor between the portion immediately below the inductor and the semiconductor substrate.

　この発明によれば、スパイラル形状の導電体層からなるシールドをインダクタの直下と半導体基板との間にインダクタに沿って設けたので、半導体基板への高周波電流の漏れが抑制され、シールドにおける径の小さい渦電流の発生が抑制される。これにより、シールドの渦電流に起因したインダクタのＱ値の劣化を低減させたインダクタ素子を実現することができる。 According to the present invention, since the shield made of the spiral conductor layer is provided along the inductor between the semiconductor substrate and the portion directly below the inductor, the leakage of the high-frequency current to the semiconductor substrate is suppressed, and the diameter of the shield is reduced. Generation of small eddy currents is suppressed. Thereby, it is possible to realize an inductor element in which the deterioration of the Q value of the inductor due to the eddy current of the shield is reduced.

この発明の実施の形態１に係るインダクタ素子の構成を示す上面図である。It is a top view which shows the structure of the inductor element which concerns on Embodiment 1 of this invention. インダクタ素子のシールドに発生する渦電流を示す図である。It is a figure which shows the eddy current which generate | occur | produces in the shield of an inductor element. 実施の形態１に係るインダクタ素子の別の構成を示す上面図である。FIG. 6 is a top view showing another configuration of the inductor element according to the first embodiment. この発明の実施の形態２に係るインダクタ素子の構成を示す上面図である。It is a top view which shows the structure of the inductor element which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係るインダクタ素子の構成を示す上面図である。It is a top view which shows the structure of the inductor element which concerns on Embodiment 3 of this invention.

　以下、この発明をより詳細に説明するため、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、この発明の実施の形態１に係るインダクタ素子１の構成を示す上面図である。インダクタ素子１は、半導体基板２、インダクタ３およびシールド４を含んで構成される。半導体基板２は、例えば、シリコン基板であり、少なくとも一方の面上にインダクタ３およびシールド４が配置される。インダクタ３は、スパイラル形状の配線層からなるインダクタである。なお、インダクタ３は、スパイラル形状であれば、その平面視が正方形、正八角形または円形であってもよい。 Hereinafter, in order to describe the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a top view showing a configuration of an inductor element 1 according to Embodiment 1 of the present invention. The inductor element 1 includes a semiconductor substrate 2, an inductor 3 and a shield 4. The semiconductor substrate 2 is, for example, a silicon substrate, and the inductor 3 and the shield 4 are disposed on at least one surface. The inductor 3 is an inductor made of a spiral wiring layer. The inductor 3 may have a square shape, a regular octagonal shape, or a circular shape as long as it has a spiral shape.

　シールド４は、インダクタ３と同じスパイラル形状の導電体層からなり、インダクタ３の直下と半導体基板２との間にインダクタ３に沿って設けられる。
　なお、図１では、シールド４がインダクタ３の直下にあることを示すため、シールド４を若干ずらして記載している。
　シールド４は、インダクタ３と同じスパイラル形状で同一の導電体層にループ経路をもたず、スパイラル形状の導電体層は、シート抵抗が十分に低い導電体で形成されてグランドに接続される。 The shield 4 is made of the same spiral conductor layer as the inductor 3, and is provided along the inductor 3 immediately below the inductor 3 and the semiconductor substrate 2.
In FIG. 1, the shield 4 is shown slightly shifted to indicate that the shield 4 is directly below the inductor 3.
The shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same conductor layer. The spiral conductor layer is formed of a conductor having a sufficiently low sheet resistance and is connected to the ground.

　半導体基板２とインダクタ３との間における寄生容量を通した半導体基板２への高周波電流の漏れは、シールド４によって抑制される。これにより、半導体基板２の抵抗成分に起因した損失が低減され、インダクタ３のＱ値の劣化を小さくすることができる。 The leakage of high-frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 is suppressed by the shield 4. Thereby, the loss resulting from the resistance component of the semiconductor substrate 2 is reduced, and deterioration of the Q value of the inductor 3 can be reduced.

　図２はインダクタ素子１のシールドに発生する渦電流を示す図である。図２に示すように、インダクタ３の周辺にあるシールド５には、インダクタ３で発生した磁界の法線成分によって径の小さい渦電流が発生する。
　これに対して、シールド４は、インダクタ３の配線層に沿ってシールド４の直下に配置されているため、インダクタ３で発生した磁界の法線成分に起因した渦電流の発生が低減される。これにより、シールド４に発生する渦電流による損失を低減することができる。 FIG. 2 is a diagram showing an eddy current generated in the shield of the inductor element 1. As shown in FIG. 2, an eddy current having a small diameter is generated in the shield 5 around the inductor 3 due to the normal component of the magnetic field generated in the inductor 3.
On the other hand, since the shield 4 is disposed directly below the shield 4 along the wiring layer of the inductor 3, the generation of eddy currents due to the normal component of the magnetic field generated in the inductor 3 is reduced. Thereby, the loss by the eddy current generated in the shield 4 can be reduced.

　シールド４は、インダクタ３よりも大きい配線幅であってもよい。
　このように構成することで、インダクタ３とシールド４とが同じ幅である場合よりも、半導体基板２への漏れ電流を抑制することができ、漏れ電流による損失を低減することができる。 The shield 4 may have a larger wiring width than the inductor 3.
By configuring in this way, the leakage current to the semiconductor substrate 2 can be suppressed and the loss due to the leakage current can be reduced as compared with the case where the inductor 3 and the shield 4 have the same width.

　前述のように、シールド４をインダクタ３の配線直下のみに設けることで、シールド４における径の小さい渦電流の発生が低減されるため、この渦電流による損失が抑制されて高いＱ値のインダクタを得ることができる。
　なお、シールド４は、インダクタ３と同じスパイラル形状を有しており、半導体基板２の同一の層にループ経路をもたない。このため、インダクタ３とシールド４とが磁気結合してシールド４に径の大きい渦電流が発生することもない。 As described above, by providing the shield 4 only immediately below the wiring of the inductor 3, the generation of eddy current with a small diameter in the shield 4 is reduced. Obtainable.
The shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same layer of the semiconductor substrate 2. For this reason, the inductor 3 and the shield 4 are not magnetically coupled, and an eddy current having a large diameter is not generated in the shield 4.

　図３は、実施の形態１における別の構成のインダクタ素子１Ａを示す上面図である。
　インダクタ素子１Ａでは、インダクタ３の周囲に配置されてグランド電位の配線層４Ａにシールド４を接続している。配線層４Ａは、インダクタ３から十分に離れた位置に配置することが望ましく、例えば、インダクタ３の配線幅の少なくとも３倍以上離れた位置に配置する。このように構成しても、上記と同様の効果を得ることができる。 FIG. 3 is a top view showing an inductor element 1A having another configuration in the first embodiment.
In the inductor element 1 </ b> A, the shield 4 is connected to the wiring layer 4 </ b> A that is disposed around the inductor 3 and has a ground potential. The wiring layer 4A is desirably disposed at a position sufficiently separated from the inductor 3, for example, disposed at a position separated by at least three times the wiring width of the inductor 3. Even if comprised in this way, the effect similar to the above can be acquired.

　以上のように、実施の形態１に係るインダクタ素子１は、半導体基板２、インダクタ３およびシールド４を備える。インダクタ３は、半導体基板２上に配置されたスパイラル形状の配線層からなる。シールド４は、インダクタ３の配線層と同じスパイラル形状の導電体層からなり、インダクタ３の直下と半導体基板２との間にインダクタ３に沿って配置される。このように構成することで、半導体基板２への高周波電流の漏れが抑制され、かつ径の小さい渦電流がシールド４に発生することも低減できる。これにより、インダクタ３のＱ値の劣化を低減させたインダクタ素子１を実現することができる。 As described above, the inductor element 1 according to the first embodiment includes the semiconductor substrate 2, the inductor 3, and the shield 4. The inductor 3 is composed of a spiral wiring layer disposed on the semiconductor substrate 2. The shield 4 is made of the same spiral conductor layer as the wiring layer of the inductor 3, and is disposed along the inductor 3 between the semiconductor substrate 2 and the portion immediately below the inductor 3. With this configuration, leakage of high-frequency current to the semiconductor substrate 2 is suppressed, and generation of eddy current having a small diameter in the shield 4 can also be reduced. Thereby, the inductor element 1 in which the deterioration of the Q value of the inductor 3 is reduced can be realized.

　実施の形態１に係るインダクタ素子１のシールド４は、インダクタ３よりも大きい配線幅である。このように構成することで、インダクタ３とシールド４とが同じ幅である場合に比べて半導体基板２への漏れ電流をさらに抑制することができ、漏れ電流による損失も低減できる。 The shield 4 of the inductor element 1 according to the first embodiment has a wiring width larger than that of the inductor 3. With this configuration, it is possible to further suppress the leakage current to the semiconductor substrate 2 as compared with the case where the inductor 3 and the shield 4 have the same width, and the loss due to the leakage current can also be reduced.

　実施の形態１に係るインダクタ素子１Ａにおいて、図３に示したように、シールド４が接地される。これにより、半導体基板２とインダクタ３との間における寄生容量を通した半導体基板２への高周波電流の漏れを抑制することができる。 In the inductor element 1A according to the first embodiment, the shield 4 is grounded as shown in FIG. Thereby, the leakage of the high frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 can be suppressed.

実施の形態２．
　図４は、この発明の実施の形態２に係るインダクタ素子１Ｂの構成を示す上面図である。インダクタ素子１Ｂは、図４に示すように、半導体基板２、インダクタ３、シールド４、配線層４Ａ、および複数のスリット６を含んで構成される。
　複数のスリット６のそれぞれは、インダクタ３の信号経路と直交する方向のスリットであり、シールド４に設けられる。 Embodiment 2. FIG.
FIG. 4 is a top view showing the configuration of the inductor element 1B according to the second embodiment of the present invention. As shown in FIG. 4, the inductor element 1 </ b> B includes a semiconductor substrate 2, an inductor 3, a shield 4, a wiring layer 4 </ b> A, and a plurality of slits 6.
Each of the plurality of slits 6 is a slit in a direction orthogonal to the signal path of the inductor 3 and is provided in the shield 4.

　インダクタ３の信号経路と直交する方向のスリット６をシールド４に設けたので、図３に示した構成よりも、インダクタ３との磁気結合によりシールド４に生じる径の大きい渦電流を抑制することができる。これにより、インダクタ３のＱ値の劣化を小さくすることが可能である。 Since the slit 6 in the direction orthogonal to the signal path of the inductor 3 is provided in the shield 4, it is possible to suppress a large-diameter eddy current generated in the shield 4 due to magnetic coupling with the inductor 3 than the configuration shown in FIG. 3. it can. Thereby, it is possible to reduce deterioration of the Q value of the inductor 3.

　なお、シールド４は、実施の形態１と同様にインダクタ３よりも大きい配線幅であってもよい。このように構成することで、インダクタ３とシールド４とが同じ幅である場合に比べて、半導体基板２への漏れ電流をさらに抑制することができ、漏れ電流による損失も低減できる。 The shield 4 may have a larger wiring width than the inductor 3 as in the first embodiment. By configuring in this way, the leakage current to the semiconductor substrate 2 can be further suppressed and the loss due to the leakage current can be reduced as compared with the case where the inductor 3 and the shield 4 have the same width.

　以上のように、実施の形態２に係るインダクタ素子１Ｂにおいて、シールド４が、インダクタ３の信号経路と直交する方向の複数のスリット６を有する。
　この構成を有することで、シールド４に生じる径の大きい渦電流を抑制でき、Ｑ値の劣化が小さいインダクタ素子１Ｂを実現することができる。 As described above, in the inductor element 1B according to the second embodiment, the shield 4 has the plurality of slits 6 in the direction orthogonal to the signal path of the inductor 3.
With this configuration, an eddy current having a large diameter generated in the shield 4 can be suppressed, and an inductor element 1B having a small Q value deterioration can be realized.

実施の形態３．
　図５はこの発明の実施の形態３に係るインダクタ素子１Ｃの構成を示す上面図である。インダクタ素子１Ｃは、半導体基板２、インダクタ３Ａ、配線層４Ａ、シールド４Ｂおよびグランド線７を含んで構成される。インダクタ３Ａは、図５に示すように、スパイラル形状の配線層を同心円状に交差させた差動インダクタである。この差動インダクタは差動回路に利用される。インダクタ３Ａでは、１つの信号がスパイラル形状の外側の配線層とスパイラル形状の内側の配線層とに差動入力されるので、外側の配線層と内側の配線層との間が高周波的に仮想接地点となる。 Embodiment 3 FIG.
FIG. 5 is a top view showing a configuration of an inductor element 1C according to the third embodiment of the present invention. The inductor element 1C includes a semiconductor substrate 2, an inductor 3A, a wiring layer 4A, a shield 4B, and a ground line 7. As shown in FIG. 5, the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected. This differential inductor is used in a differential circuit. In the inductor 3A, one signal is differentially input to the outer wiring layer of the spiral shape and the inner wiring layer of the spiral shape, so that the virtual connection between the outer wiring layer and the inner wiring layer is virtually performed. It becomes a point.

　シールド４Ｂは、インダクタ３Ａと同じスパイラル形状の導電体層からなり、インダクタ３Ａの直下と半導体基板２との間にインダクタ３Ａに沿って配置される。
　グランド線７は、インダクタ３Ａにおける外側の配線層と内側の配線層との間に配置されて、インダクタ３Ａの仮想接地点とグランド電位の配線層４Ａとを接続する。グランド線７は、シールド４Ｂにも接続されている。
　インダクタ３Ａの周囲にある配線層４Ａとシールド４Ｂとをグランド線７で接続することにより、半導体基板２への漏れ電流による損失を低減することができる。
　また、シールド４Ｂは、インダクタ３Ａの配線直下のみに配置されるため、インダクタ３Ａの磁界による小さな渦電流の発生も低減される。これにより、この渦電流による損失も低減される。 The shield 4B is made of the same spiral conductor layer as that of the inductor 3A, and is disposed along the inductor 3A between the semiconductor substrate 2 and immediately below the inductor 3A.
The ground line 7 is disposed between the outer wiring layer and the inner wiring layer in the inductor 3A, and connects the virtual ground point of the inductor 3A and the wiring layer 4A having the ground potential. The ground line 7 is also connected to the shield 4B.
By connecting the wiring layer 4 </ b> A around the inductor 3 </ b> A and the shield 4 </ b> B with the ground line 7, loss due to leakage current to the semiconductor substrate 2 can be reduced.
Further, since the shield 4B is disposed only immediately below the wiring of the inductor 3A, the generation of small eddy currents due to the magnetic field of the inductor 3A is reduced. Thereby, the loss by this eddy current is also reduced.

　なお、実施の形態２と同様に、インダクタ３Ａの配線と直交する方向の複数のスリット６をシールド４Ｂに設けてもよい。
　また、シールド４Ｂは、実施の形態１と同様に、インダクタ３Ａよりも大きい配線幅であってもよい。 Similar to the second embodiment, a plurality of slits 6 in a direction orthogonal to the wiring of the inductor 3A may be provided in the shield 4B.
Further, the shield 4B may have a larger wiring width than the inductor 3A, as in the first embodiment.

　以上のように、実施の形態３に係るインダクタ素子１Ｃにおいて、インダクタ３Ａは、スパイラル形状の配線層を同心円状に交差させた差動インダクタである。
　インダクタ３Ａの直下と半導体基板２との間には、インダクタ３Ａに沿ったスパイラル形状の導電体層からなるシールド４Ｂが配置されている。インダクタ３Ａは、仮想接地点がシールド４Ｂに接続されている。
　実施の形態１と同様に、半導体基板２とインダクタ３Ａとの間にシールド４Ｂを配置したので、半導体基板２への漏れ電流を抑制することができる。
　シールド４Ｂは、インダクタ３Ａの配線直下に配置されるので、インダクタ３Ａで発生した磁界がシールド４Ｂを貫通することがなく、小さな渦電流がシールド４Ｂに発生することも抑制される。これにより、渦電流に起因した損失が低減され、Ｑ値の劣化が小さいインダクタ素子１Ｃを実現することができる。 As described above, in the inductor element 1C according to the third embodiment, the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected.
A shield 4B made of a spiral conductor layer along the inductor 3A is disposed between the semiconductor substrate 2 and the part directly under the inductor 3A. Inductor 3A has a virtual ground point connected to shield 4B.
Similar to the first embodiment, since the shield 4B is disposed between the semiconductor substrate 2 and the inductor 3A, the leakage current to the semiconductor substrate 2 can be suppressed.
Since the shield 4B is disposed immediately below the wiring of the inductor 3A, the magnetic field generated by the inductor 3A does not penetrate the shield 4B, and the generation of a small eddy current in the shield 4B is also suppressed. As a result, it is possible to realize an inductor element 1C in which loss due to eddy current is reduced and Q value is less deteriorated.

　なお、本発明はその発明の範囲内において、各実施の形態の自由な組み合わせあるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, a free combination of each embodiment, a modification of an arbitrary component of each embodiment, or an omission of any component in each embodiment is possible.

　この発明に係るインダクタ素子はＱ値の劣化が小さいので、高周波回路に好適である。 The inductor element according to the present invention is suitable for a high-frequency circuit because the deterioration of the Q value is small.

　１，１Ａ～１Ｃ　インダクタ素子、２　半導体基板、３，３Ａ　インダクタ、４，４Ｂ，５　シールド、４Ａ　配線層、６　スリット、７　グランド線。 1, 1A to 1C inductor element, 2 semiconductor substrate, 3, 3A inductor, 4, 4B, 5 shield, 4A wiring layer, 6 slits, 7 ground lines.

Claims (6)

　半導体基板と、
　前記半導体基板上に配置されたスパイラル形状の配線層からなるインダクタと、
　前記インダクタの配線層と同じスパイラル形状の導電体層からなり、前記インダクタの直下と前記半導体基板との間に前記インダクタに沿って配置されたシールドと
　を備えたことを特徴とするインダクタ素子。 A semiconductor substrate;
An inductor composed of a spiral wiring layer disposed on the semiconductor substrate;
An inductor element comprising: a conductor layer having a spiral shape that is the same as the wiring layer of the inductor, and a shield disposed along the inductor between the portion immediately below the inductor and the semiconductor substrate. 　前記シールドは、接地されていること
　を特徴とする請求項１記載のインダクタ素子。 The inductor element according to claim 1, wherein the shield is grounded. 　前記シールドは、前記インダクタよりも大きい配線幅であること
　を特徴とする請求項１記載のインダクタ素子。 The inductor element according to claim 1, wherein the shield has a wiring width larger than that of the inductor. 　前記インダクタは、スパイラル形状の配線層を同心円状に交差させた差動インダクタであること
　を特徴とする請求項１記載のインダクタ素子。 2. The inductor element according to claim 1, wherein the inductor is a differential inductor in which spiral wiring layers are concentrically intersected. 　前記差動インダクタは、仮想接地点が前記シールドに接続されていること
　を特徴とする請求項４記載のインダクタ素子。 The inductor element according to claim 4, wherein a virtual ground point of the differential inductor is connected to the shield. 　前記シールドは、前記インダクタの信号経路と直交する方向に複数のスリットを有すること
　を特徴とする請求項１記載のインダクタ素子。 The inductor element according to claim 1, wherein the shield has a plurality of slits in a direction orthogonal to a signal path of the inductor.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020139457A1 (en) * 2018-12-28 2020-07-02 Intel Corporation Reduction of ohmic losses in monolithic chip inductors and transformers of radio frequency integrated circuits

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310533A (en) * 2005-04-28 2006-11-09 Matsushita Electric Ind Co Ltd Inductor element
JP2007019071A (en) * 2005-07-05 2007-01-25 Seiko Epson Corp Electronic substrate manufacturing method, electronic substrate, and electronic device
JP2010192500A (en) * 2009-02-16 2010-09-02 Seiko Epson Corp Semiconductor device
JP2011035409A (en) * 2003-05-16 2011-02-17 Panasonic Corp Mutual induction circuit
JP2011518433A (en) * 2008-04-03 2011-06-23 クゥアルコム・インコーポレイテッド Inductor with patterned ground plane

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011035409A (en) * 2003-05-16 2011-02-17 Panasonic Corp Mutual induction circuit
JP2006310533A (en) * 2005-04-28 2006-11-09 Matsushita Electric Ind Co Ltd Inductor element
JP2007019071A (en) * 2005-07-05 2007-01-25 Seiko Epson Corp Electronic substrate manufacturing method, electronic substrate, and electronic device
JP2011518433A (en) * 2008-04-03 2011-06-23 クゥアルコム・インコーポレイテッド Inductor with patterned ground plane
JP2010192500A (en) * 2009-02-16 2010-09-02 Seiko Epson Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020139457A1 (en) * 2018-12-28 2020-07-02 Intel Corporation Reduction of ohmic losses in monolithic chip inductors and transformers of radio frequency integrated circuits
US10930588B2 (en) 2018-12-28 2021-02-23 Intel Corporation Reduction of ohmic losses in monolithic chip inductors and transformers of radio frequency integrated circuits

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