[go: up one dir, main page]

WO2018122949A1 - Élément inducteur - Google Patents

Élément inducteur Download PDF

Info

Publication number
WO2018122949A1
WO2018122949A1 PCT/JP2016/088860 JP2016088860W WO2018122949A1 WO 2018122949 A1 WO2018122949 A1 WO 2018122949A1 JP 2016088860 W JP2016088860 W JP 2016088860W WO 2018122949 A1 WO2018122949 A1 WO 2018122949A1
Authority
WO
WIPO (PCT)
Prior art keywords
inductor
shield
semiconductor substrate
inductor element
wiring layer
Prior art date
Application number
PCT/JP2016/088860
Other languages
English (en)
Japanese (ja)
Inventor
萩原　達也
孝信 藤原
下沢　充弘
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2016/088860 priority Critical patent/WO2018122949A1/fr
Publication of WO2018122949A1 publication Critical patent/WO2018122949A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to an inductor element disposed on a semiconductor substrate on which a high-frequency circuit is integrated.
  • inductor elements are used in high-frequency circuits.
  • a spiral-shaped inductor is disposed on a conductive silicon substrate, high-frequency current leaks to the silicon substrate through a parasitic capacitance between the inductor and the silicon substrate, and loss occurs due to the resistance component of the silicon substrate. to degrade.
  • a conductive shield is disposed between the spiral-shaped inductor and the silicon substrate. This shield suppresses leakage of high-frequency current to the silicon substrate through the parasitic capacitance, so that deterioration of the Q value of the inductor is reduced.
  • an eddy current having a large diameter flows in the winding direction due to the magnetic field generated in the inductor through the conductive shield.
  • the generation of a large eddy current is suppressed by providing a plurality of slits in a direction orthogonal to the inductor wiring.
  • Non-Patent Document 1 a shield is formed on the entire surface between the inductor and the silicon substrate. For this reason, the magnetic field generated in the inductor penetrates the shield around it, and an eddy current having a small diameter flows through the shield. This eddy current has a problem that the Q value of the inductor deteriorates.
  • the present invention solves the above-described problems, and an object of the present invention is to obtain an inductor element that can suppress the generation of eddy current in a shield and reduce the deterioration of the Q value of the inductor.
  • An inductor element includes a semiconductor substrate, an inductor, and a shield.
  • the inductor is composed of a spiral wiring layer disposed on a semiconductor substrate.
  • the shield is made of a conductor layer having the same spiral shape as the wiring layer of the inductor, and is disposed along the inductor between the portion immediately below the inductor and the semiconductor substrate.
  • the shield made of the spiral conductor layer is provided along the inductor between the semiconductor substrate and the portion directly below the inductor, the leakage of the high-frequency current to the semiconductor substrate is suppressed, and the diameter of the shield is reduced. Generation of small eddy currents is suppressed. Thereby, it is possible to realize an inductor element in which the deterioration of the Q value of the inductor due to the eddy current of the shield is reduced.
  • FIG. 6 is a top view showing another configuration of the inductor element according to the first embodiment. It is a top view which shows the structure of the inductor element which concerns on Embodiment 2 of this invention. It is a top view which shows the structure of the inductor element which concerns on Embodiment 3 of this invention.
  • FIG. 1 is a top view showing a configuration of an inductor element 1 according to Embodiment 1 of the present invention.
  • the inductor element 1 includes a semiconductor substrate 2, an inductor 3 and a shield 4.
  • the semiconductor substrate 2 is, for example, a silicon substrate, and the inductor 3 and the shield 4 are disposed on at least one surface.
  • the inductor 3 is an inductor made of a spiral wiring layer.
  • the inductor 3 may have a square shape, a regular octagonal shape, or a circular shape as long as it has a spiral shape.
  • the shield 4 is made of the same spiral conductor layer as the inductor 3, and is provided along the inductor 3 immediately below the inductor 3 and the semiconductor substrate 2. In FIG. 1, the shield 4 is shown slightly shifted to indicate that the shield 4 is directly below the inductor 3.
  • the shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same conductor layer.
  • the spiral conductor layer is formed of a conductor having a sufficiently low sheet resistance and is connected to the ground.
  • the leakage of high-frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 is suppressed by the shield 4. Thereby, the loss resulting from the resistance component of the semiconductor substrate 2 is reduced, and deterioration of the Q value of the inductor 3 can be reduced.
  • FIG. 2 is a diagram showing an eddy current generated in the shield of the inductor element 1.
  • an eddy current having a small diameter is generated in the shield 5 around the inductor 3 due to the normal component of the magnetic field generated in the inductor 3.
  • the shield 4 is disposed directly below the shield 4 along the wiring layer of the inductor 3, the generation of eddy currents due to the normal component of the magnetic field generated in the inductor 3 is reduced. Thereby, the loss by the eddy current generated in the shield 4 can be reduced.
  • the shield 4 may have a larger wiring width than the inductor 3.
  • the shield 4 has the same spiral shape as the inductor 3 and does not have a loop path in the same layer of the semiconductor substrate 2. For this reason, the inductor 3 and the shield 4 are not magnetically coupled, and an eddy current having a large diameter is not generated in the shield 4.
  • FIG. 3 is a top view showing an inductor element 1A having another configuration in the first embodiment.
  • the shield 4 is connected to the wiring layer 4 ⁇ / b> A that is disposed around the inductor 3 and has a ground potential.
  • the wiring layer 4A is desirably disposed at a position sufficiently separated from the inductor 3, for example, disposed at a position separated by at least three times the wiring width of the inductor 3. Even if comprised in this way, the effect similar to the above can be acquired.
  • the inductor element 1 includes the semiconductor substrate 2, the inductor 3, and the shield 4.
  • the inductor 3 is composed of a spiral wiring layer disposed on the semiconductor substrate 2.
  • the shield 4 is made of the same spiral conductor layer as the wiring layer of the inductor 3, and is disposed along the inductor 3 between the semiconductor substrate 2 and the portion immediately below the inductor 3.
  • the shield 4 of the inductor element 1 according to the first embodiment has a wiring width larger than that of the inductor 3. With this configuration, it is possible to further suppress the leakage current to the semiconductor substrate 2 as compared with the case where the inductor 3 and the shield 4 have the same width, and the loss due to the leakage current can also be reduced.
  • the shield 4 is grounded as shown in FIG. Thereby, the leakage of the high frequency current to the semiconductor substrate 2 through the parasitic capacitance between the semiconductor substrate 2 and the inductor 3 can be suppressed.
  • FIG. FIG. 4 is a top view showing the configuration of the inductor element 1B according to the second embodiment of the present invention.
  • the inductor element 1 ⁇ / b> B includes a semiconductor substrate 2, an inductor 3, a shield 4, a wiring layer 4 ⁇ / b> A, and a plurality of slits 6.
  • Each of the plurality of slits 6 is a slit in a direction orthogonal to the signal path of the inductor 3 and is provided in the shield 4.
  • the slit 6 in the direction orthogonal to the signal path of the inductor 3 is provided in the shield 4, it is possible to suppress a large-diameter eddy current generated in the shield 4 due to magnetic coupling with the inductor 3 than the configuration shown in FIG. 3. it can. Thereby, it is possible to reduce deterioration of the Q value of the inductor 3.
  • the shield 4 may have a larger wiring width than the inductor 3 as in the first embodiment.
  • the shield 4 has the plurality of slits 6 in the direction orthogonal to the signal path of the inductor 3. With this configuration, an eddy current having a large diameter generated in the shield 4 can be suppressed, and an inductor element 1B having a small Q value deterioration can be realized.
  • FIG. 5 is a top view showing a configuration of an inductor element 1C according to the third embodiment of the present invention.
  • the inductor element 1C includes a semiconductor substrate 2, an inductor 3A, a wiring layer 4A, a shield 4B, and a ground line 7.
  • the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected. This differential inductor is used in a differential circuit.
  • one signal is differentially input to the outer wiring layer of the spiral shape and the inner wiring layer of the spiral shape, so that the virtual connection between the outer wiring layer and the inner wiring layer is virtually performed. It becomes a point.
  • the shield 4B is made of the same spiral conductor layer as that of the inductor 3A, and is disposed along the inductor 3A between the semiconductor substrate 2 and immediately below the inductor 3A.
  • the ground line 7 is disposed between the outer wiring layer and the inner wiring layer in the inductor 3A, and connects the virtual ground point of the inductor 3A and the wiring layer 4A having the ground potential.
  • the ground line 7 is also connected to the shield 4B.
  • a plurality of slits 6 in a direction orthogonal to the wiring of the inductor 3A may be provided in the shield 4B. Further, the shield 4B may have a larger wiring width than the inductor 3A, as in the first embodiment.
  • the inductor 3A is a differential inductor in which spiral wiring layers are concentrically intersected.
  • a shield 4B made of a spiral conductor layer along the inductor 3A is disposed between the semiconductor substrate 2 and the part directly under the inductor 3A.
  • Inductor 3A has a virtual ground point connected to shield 4B. Similar to the first embodiment, since the shield 4B is disposed between the semiconductor substrate 2 and the inductor 3A, the leakage current to the semiconductor substrate 2 can be suppressed.
  • the shield 4B is disposed immediately below the wiring of the inductor 3A, the magnetic field generated by the inductor 3A does not penetrate the shield 4B, and the generation of a small eddy current in the shield 4B is also suppressed. As a result, it is possible to realize an inductor element 1C in which loss due to eddy current is reduced and Q value is less deteriorated.
  • the inductor element according to the present invention is suitable for a high-frequency circuit because the deterioration of the Q value is small.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un élément inducteur (1) comprenant un substrat semiconducteur (2), un inducteur (3) composé d'une couche de fil en forme de spirale et disposée sur le substrat semiconducteur (2), et un blindage (4) composé d'une couche conductrice sous la même forme de spirale que la couche de fil de l'inducteur (3) et disposé le long de l'inducteur (3) entre une région située immédiatement en-dessous de l'inducteur (3) et le substrat semiconducteur (2).
PCT/JP2016/088860 2016-12-27 2016-12-27 Élément inducteur WO2018122949A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/088860 WO2018122949A1 (fr) 2016-12-27 2016-12-27 Élément inducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/088860 WO2018122949A1 (fr) 2016-12-27 2016-12-27 Élément inducteur

Publications (1)

Publication Number Publication Date
WO2018122949A1 true WO2018122949A1 (fr) 2018-07-05

Family

ID=62707118

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/088860 WO2018122949A1 (fr) 2016-12-27 2016-12-27 Élément inducteur

Country Status (1)

Country Link
WO (1) WO2018122949A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020139457A1 (fr) * 2018-12-28 2020-07-02 Intel Corporation Réduction des pertes ohmiques dans des bobines d'inductance et des transformateurs de puces monolithiques de circuits intégrés radiofréquence

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310533A (ja) * 2005-04-28 2006-11-09 Matsushita Electric Ind Co Ltd インダクタ素子
JP2007019071A (ja) * 2005-07-05 2007-01-25 Seiko Epson Corp 電子基板の製造方法、電子基板および電子機器
JP2010192500A (ja) * 2009-02-16 2010-09-02 Seiko Epson Corp 半導体装置
JP2011035409A (ja) * 2003-05-16 2011-02-17 Panasonic Corp 相互誘導回路
JP2011518433A (ja) * 2008-04-03 2011-06-23 クゥアルコム・インコーポレイテッド パターン化された接地平面を有するインダクタ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011035409A (ja) * 2003-05-16 2011-02-17 Panasonic Corp 相互誘導回路
JP2006310533A (ja) * 2005-04-28 2006-11-09 Matsushita Electric Ind Co Ltd インダクタ素子
JP2007019071A (ja) * 2005-07-05 2007-01-25 Seiko Epson Corp 電子基板の製造方法、電子基板および電子機器
JP2011518433A (ja) * 2008-04-03 2011-06-23 クゥアルコム・インコーポレイテッド パターン化された接地平面を有するインダクタ
JP2010192500A (ja) * 2009-02-16 2010-09-02 Seiko Epson Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020139457A1 (fr) * 2018-12-28 2020-07-02 Intel Corporation Réduction des pertes ohmiques dans des bobines d'inductance et des transformateurs de puces monolithiques de circuits intégrés radiofréquence
US10930588B2 (en) 2018-12-28 2021-02-23 Intel Corporation Reduction of ohmic losses in monolithic chip inductors and transformers of radio frequency integrated circuits

Similar Documents

Publication Publication Date Title
JP6222410B1 (ja) Ｅｓｄ保護回路、差動伝送線路、コモンモードフィルタ回路、ｅｓｄ保護デバイスおよび複合デバイス
US8416022B2 (en) Power amplifier device
JP5180625B2 (ja) 半導体装置
CN104051438B (zh) 具有耦合器的半导体芯片配置
US9209130B2 (en) Semiconductor device having ground shield structure and fabrication method thereof
JP5551480B2 (ja) 半導体装置および半導体装置の製造方法
US10886730B2 (en) Filter having an ESD protection device
US20160126925A1 (en) Semiconductor resonators with reduced substrate losses
CN106024340A (zh) 具有屏蔽结构的变压器
KR20110129331A (ko) 집적 회로 인덕터 구조체, 전자 시스템 및 집적 회로 인덕터 사이의 자기 커플링 감소 방법
WO2018122949A1 (fr) Élément inducteur
JP5177387B2 (ja) インダクタ用シールドおよびシールド付きインダクタ
CN108269799B (zh) 磁环境中的物理设计
JP6376623B2 (ja) コモンモードフィルター
TWI749398B (zh) 電感電容振盪器及共模共振腔
JP5864985B2 (ja) スパイラルアンテナとその素子終端処理方法
JP2004095777A (ja) インダクタ素子
CN112582379B (zh) 图案化屏蔽结构
JP2005236033A (ja) 半導体装置
JP2006310533A (ja) インダクタ素子
CN109428141B (zh) 平衡非平衡转换器
US10748860B2 (en) Amplifier
JP6699499B2 (ja) フィルタ
KR20070060615A (ko) 고성능 집적형 인덕터
WO2015132958A1 (fr) Circuit d'adaptation d'entrée/sortie

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16925076

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16925076

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP